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參數(shù)資料
| 型號(hào)： | AD9773 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
| 中文描述： | 12位，160 MSPS的2】/ 4】/ 8】TxDAC系列插雙D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大?。?/td> | 218K |
| 代理商： | AD9773 |
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AD9773–SPECIFICATIONS
PIN FUNCTION DESCRIPTIONS
7
PRELIMINARY TECHNICAL DATA
Pin No.
Name
Descripti
on
73,72
I
OUTA1
, I
OUTB1
I
OUTA2
, I
OUTB2
REFIO
FSADJ1
FSADJ2
Differential DAC
c
urrent outputs, I Channel
69,68
58
60
59
Differential DAC
c
urrent outputs, Q Channel
Reference output, 1.2V nominal
Full-scale current adjust, I channel
Full-scale current adjust, Q channel
5
6
8
CLK+
CLK-
DATACLK/PLL_LOCK
Differential Clock input
Differential Clock input
With the PLL enabled, this pin indicates the state of the PLL. A
read of a logic 1 indicates the PLL is in the locked state. Logic
0 indicates the PLL has not achieved lock. With the PLL dis-
abled, and the AD9773 in two port mode, this pin becomes a
clock signal, running at the input data rate, which may either be
input to the AD9773, or generated by the AD9773, depending
on the state of address 2h, bit 3 in the SPI control register.
PLL Loop Filter
Logic one resets all of the SPI port registers, including address
0h, to their default values. A software reset can also be done
by writing a logic one to SPI register 0h, bit 5. However, the
software reset has no effect on the bits in address 0h.
Port 1 data inputs
In one port mode, IQSEL = 1 followed by a rising edge of the
differential input clock will latch the data into the I channel
input register. IQSEL = 0 will latch the data into the Q
channel input register. In two port mode, this pin becomes the
port 2 MSB.
With the PLL disabled, and the AD9773 in one port mode, this
pin becomes a clock output which runs at twice the input data
rate of the I and Q channels. This allows the AD9773 to accept
and demux interleaved I and Q data to the I and Q input reg-
isters.
Port 2 data inputs.
2
57
LPF
RESET
11-16,19-24
31
P1B11 to P1B0
IQSEL/P2B15
32
ONEPORTCLK/P2B14
33,34,37-42,45,46
P2B11 to P2B0
56
SPI_CSB
Chip select/SPI data synchronization. On momentary logic
high, resets SPI port logic and initializes instruction cycle.
Data input to the SPI port is registered on the rising edge of
SPI_CLK. Data output on the SPI port is registered on the
falling edge.
Bidirectional data pin. Data direction is controlled by bit 7 of
register address 0h. The default setting for this bit is 0, which
sets SDIO as an input.
In the case where SDIO is an input, SDO acts as an output.
When SDIO becomes an output, SDO enters a high Z state.
55
SPI_CLK
54
SPI_SDIO
53
SPI_SDO
79,77,75,74,71,70,
67,66,64,62
80.78.76,65,63,61
ACOM
AVDD
Analog Common
Analog Supply Voltage
51,43,36,26,17,10
52,44,35,25,18,9
DVDD
DCOM
Digital Supply Voltage
Digital Common
1,3
4,7
CLKVDD
CLKCOM
Clock Supply Voltage
Clock Supply Common
REV. PrA
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| AD9773AST | 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9773AST | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
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| AD9773BSVZ | 功能描述:IC DAC 12BIT DUAL 160MSPS 80TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱(chēng):MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9773BSVZRL | 功能描述:IC DAC 12BIT DUAL 160MSPS 80TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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