參數(shù)資料
型號： AD9772AASTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 13/40頁
文件大?。?/td> 0K
描述： IC DAC 14BIT 160MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準包裝： 2,000
系列： TxDAC+®
設(shè)置時間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 272mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 160M
AD9772A
Rev. C | Page 20 of 40
The PLL clock multiplier has two modes of operation. It can be
enabled for less demanding applications, providing a reference
clock meeting the minimum specified input data rate of 6 MSPS.
Alternatively, it can be disabled for applications below this data
rate or for applications requiring higher phase noise performance.
In this case, a reference clock must be provided at twice the input
data rate (that is, 2 × fDATA) without the zero-stuffing option selected
or at four times the input data rate (that is, 4 × fDATA) with the zero-
stuffing option selected. Note that multiple AD9772A devices
can be synchronized in either mode if driven by the same reference
clock because the PLL clock multiplier, when enabled, ensures
synchronization. RESET can be used for synchronization if the
PLL clock multiplier is disabled.
Figure 30 shows the proper configuration used to enable the
PLL clock multiplier. In this case, the external clock source is
applied to CLK+ (and/or CLK) and the PLL clock multiplier is
fully enabled by connecting PLLVDD to CLKVDD.
The settling/acquisition time characteristics of the PLL are also
dependent on the divide-by-N ratio as well as the input data
rate. In general, the acquisition time increases with increasing
data rate (for fixed divide-by-N ratio) or with an increasing
divide-by-N ratio (for fixed input data rate).
Because the VCO can operate over a 96 MHz to 400 MHz
range, the prescaler divide-by-ratio following the VCO must be
set according to Table 10 for a given input data rate (that is,
fDATA) to ensure optimum phase noise and successful locking. In
general, the best phase noise performance for any prescaler
setting is achieved with the VCO operating near its maximum
output frequency of 400 MHz. Note that the divide-by-N ratio
also depends on whether the zero-stuffing option is enabled
because this option requires the DAC to operate at 4× the input
data rate. The divide-by-N ratio is set by DIV1 and DIV0.
With the PLL clock multiplier enabled, PLLLOCK serves as an
active high control output that can be monitored upon system
power-up to indicate that the PLL is successfully locked to the
input clock. Note that when the PLL clock multiplier is not
locked, PLLLOCK toggles between logic high and low in an
asynchronous manner until locking is finally achieved. As a
result, it is recommended that PLLLOCK, if monitored, be
sampled several times to detect proper locking 100 ms after
power-up.
Table 10. Recommended Prescaler Divide-by-N Ratio Settings
fDATA
(MSPS)
MOD1
DIV1
DIV0
Divide-by-N Ratio
48 to 160
0
1
24 to 100
0
1
2
12 to 50
0
1
0
4
6 to 25
0
1
8
24 to 100
1
0
1
12 to 50
1
0
1
2
6 to 25
1
0
4
3 to 12.5
1
8
As previously stated, applications requiring input data rates
below 6 MSPS must disable the PLL clock multiplier and
provide an external reference clock. However, for applications
already containing a low phase noise (that is, low jitter) reference
clock that is twice (or four times) the input data rate, users should
consider disabling the PLL clock multiplier to achieve the best SNR
performance from the AD9772A. Note that the SFDR performance
and wideband noise performance of the AD9772A remain
unaffected with or without the PLL clock multiplier enabled.
The effects of phase noise on the AD9772A SNR performance
become more noticeable at higher reconstructed output fre-
quencies and signal levels. Figure 31 compares the phase noise
of a full-scale sine wave at exactly fDATA/4 for different data rates
(and therefore carrier frequencies) with the optimum DIV1 and
DIV0 settings. The effects of phase noise, and its effect on a
signal’s CNR performance, become even more evident at higher
IF frequencies, as shown in Figure 32. In both instances, it is the
narrow-band phase noise that limits the CNR performance.
PLL ENABLED,
fDATA = 50MSPS
FREQUENCY OFFSET (MHz)
0
–10
–110
0
NO
IS
E
D
E
NS
IT
Y
(d
B
m
/Hz
)
–30
–50
–70
–90
12
3
4
–100
–80
–60
–40
–20
5
PLL ENABLED,
fDATA = 50MSPS
PLL ENABLED,
fDATA = 75MSPS
PLL ENABLED,
fDATA = 100MSPS
PLL ENABLED,
fDATA = 160MSPS
02
25
3
-03
1
Figure 31. Phase Noise of PLL Clock Multiplier with a Full-Scale Sine Wave at
Exactly fOUT = fDATA/4 for Different fDATA Settings with Optimum DIV0/DIV1
Settings Using the Rohde & Schwarz FSEA30, RBW = 30 kHz
FREQUENCY (MHz)
10
–10
–110
120
AM
P
L
IT
UDE
(
d
Bm
)
–30
–50
–70
–90
122
124
126
128
130
0
22
53
-03
2
Figure 32. Direct IF Mode Reveals Phase Noise Degradation with and
Without PLL Clock Multiplier (IF = 125 MHz and fDATA = 100 MSPS)
To disable the PLL clock multiplier, connect PLLVDD to
PLLCOM as shown in Figure 33. LPF can then remain open
because this portion of the PLL circuitry is disabled. The
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9772A-EB 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk
AD9772A-EBZ 功能描述:BOARD EVAL FOR AD9772A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9772AST 制造商:Rochester Electronics LLC 功能描述:14 BIT DAC W/2X INTERPOLA - Tape and Reel
AD9772EB 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter
AD9773 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
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