參數(shù)資料
型號(hào)： AD9772A-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/40頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9772A
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
DAC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 160M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時(shí)間： 11ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9772A
AD9772A
Rev. C | Page 10 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
SLEEP
LPF
PLLVDD
PLLCOM
CLKVDD
CLKCOM
CLK–
DCOM
(MSB) DB13
DB12
DB11
DB10
DB9
NC = NO CONNECT
DB8
DB7
DB6
DB5
CLK+
DIV0
DIV1
RESET
AD9772A
DB4
PLLLOCK
DV
D
DV
D
AV
D
AV
D
ACO
M
I OU
T
A
IOU
T
B
ACO
M
FS
A
D
J
RE
F
IO
RE
F
L
O
ACO
M
DB
3
DB
2
DB
1
(L
S
B
)DB0
MO
D
0
MO
D
1
DCO
M
DCO
M
DV
D
DV
D
NC
0
22
53
-00
6
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 19, 20
DCOM
Digital Common.
3
DB13
Most Significant Data Bit (MSB).
4 to 15
DB12 to DB1
Data Bit 1 to Data Bit 12.
16
DB0
Least Significant Data Bit (LSB).
17
MOD0
Digital High-Pass Filter Response. Active high. This pin invokes the digital high-pass filter response (that is,
half-wave digital mixing mode). Note that quarter-wave digital mixing occurs if this pin and the MOD1 pin
are set high.
18
MOD1
Zero-Stuffing Mode. Active high. This pin invokes zero-stuffing mode. Note that quarter-wave digital mixing
occurs if this pin and the MOD0 pin are set high.
23, 24
NC
No Connect. Leave open.
21, 22, 47, 48
DVDD
Digital Supply Voltage (3.1 V to 3.5 V).
25
PLLLOCK
Lock Signal of the Phase-Lock Loop. This pin provides the lock signal of the phase-lock loop when the PLL
clock multiplier is enabled, and provides the 1× clock output when the PLL clock multiplier is disabled. High
indicates that PLL is locked to the input clock. The maximum fanout is 1 (that is, <10 pF).
26
RESET
Internal Divider Reset. This pin can reset the internal driver to synchronize the internal 1× clock to the input
data and/or multiple AD9772A devices. The reset is initiated if this pin is momentarily brought high when
PLL is disabled.
27, 28
DIV1, DIV0
PLL Prescaler Divide Ratio. DIV1 and DIV0 set the prescaler divide ratio of the PLL (refer to Table 10).
29
CLK+
Noninverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
30
CLK
Inverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
31
CLKCOM
Clock Input Common.
32
CLKVDD
Clock Input Supply Voltage (3.1 V to 3.5 V).
33
PLLCOM
Phase-Lock Loop Common.
34
PLLVDD
Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable the PLL clock multiplier, connect PLLVDD to
PLLCOM.
35
LPF
PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than
10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated in Figure 61.
36
SLEEP
Power-Down Control Input. Active high. When this pin is not used, connect it to ACOM.
37, 41, 44
ACOM
Analog Common.
38
REFLO
Reference Ground When Internal 1.2 V Reference Is Used. Connect this pin to AVDD to disable the internal
reference.
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