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參數(shù)資料
| 型號： | AD976 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters(100kSPS 16位A/D轉(zhuǎn)換器) |
| 中文描述： | 16位，100 kSPS/200 kSPS的BiCMOS工藝的A / D轉(zhuǎn)換器（100ksps的16位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 200K |
| 代理商： | AD976 |
AD976/AD976A
–8–
REV. B
DATA
VALID
t
6
t
3
t
1
t
10
t
9
CONVERT
CONVERT
ACQUIRE
MODE
DATA
BUS
HI-Z
NOT
VALID
HI-Z
DATA
VALID
BUSY
R/
C
t
7
t
8
t
11
t
13
ACQUIRE
t
2
t
4
PREVIOUS
DATA VALID
t
5
PREVIOUS
DATA VALID
t
14
Figure 2. Conversion Timing with Outputs Enabled After Conversion (
CS
Tied Low)
MODE
BUSY
R/
C
DATA
BUS
CS
t
6
t
12
t
1
CONVERT
ACQUIRE
HI-Z
DATA VALID
t
7
ACQUIRE
t
9
t
12
t
12
t
12
t
1
t
3
t
4
t
14
HI-Z
Figure 3. Using
CS
to Control Conversion and Read Timing
CONVERSION CONTROL
The AD976/AD976A is controlled by two signals: R/
C
and
CS
,
as shown in Figures 2 and 3. To initiate a conversion and place
the sample/hold circuit into the hold state, both the R/
C
and
CS
signals must be brought low for no less than 50 ns. Once the
conversion process begins, the
BUSY
signal will go Low until
the conversion is complete. At the end of a conversion,
BUSY
will return High, and the resulting valid data will be available on
the data bus. On the first conversion after the AD976/AD976A
is powered up, the DATA output will be indeterminate.
The AD976/AD976A exhibits two modes of conversion. In the
mode demonstrated in Figure 2, conversion timing is controlled
by a negative-going R/
C
signal, at least 50 ns wide. In this mode
the
CS
pin is always tied low, and the only limit placed on how
long the R/
C
signal can remain low is the desired sampling rate.
Less than 83 ns after the initiation of a conversion, the
BUSY
signal will be brought low and remain low until the conversion is
complete and the output shift registers have been updated with
the new Binary Twos Complement data.
Figure 3 demonstrates the AD976/AD976A conversion timing,
using
CS
to control both the conversion process and the reading
of output data. To operate in this mode, the R/
C
signal should
be brought low no less than 10 ns before the falling edge of a
CS
pulse (50 ns wide) is applied to the ADC. Once these two pulses
are applied,
BUSY
will go low and remain low until a conver-
sion is complete. After a maximum of 4
μ
s (AD976A only),
BUSY
will again return high, and parallel data will be valid on
the ADC outputs. To achieve the maximum 100 kHz/200 kHz
throughput rate of the part, the negative going R/
C
and
CS
control signals should be applied every 5
μ
s (AD976A). It should
also be noted that although all R/
C
and
CS
commands will be
ignored once a conversion has begun, these inputs can be
asserted during a conversion; i.e., a read during conversion can
be performed. Voltage transients on these inputs could feed
through to the analog circuitry and affect conversion results.
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