參數(shù)資料
型號: AD9764-EB
廠商: Analog Devices, Inc.
英文描述: 14-Bit, 125 MSPS TxDAC D/A Converter
中文描述: 14位,125 MSPS的TxDAC系列D / A轉(zhuǎn)換
文件頁數(shù): 5/22頁
文件大?。?/td> 307K
代理商: AD9764-EB
REV. B
AD9764
–5–
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9764
NC = NO CONNECT
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
I
OUTA
I
OUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
2–13
14
15
DB13
DB12–DB1 Data Bits 1–12.
DB0
Least Significant Data Bit (LSB).
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if
not used.
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1
μ
F capacitor to ACOM when internal reference activated.
FS ADJ
Full-Scale Current Output Adjust.
COMP1
Bandwidth/Noise Reduction Node. Add 0.1
μ
F to AVDD for optimum performance.
ACOM
Analog Common.
I
OUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
I
OUTA
DAC Current Output. Full-scale current when all data bits are 1s.
COMP2
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
μ
F capacitor.
AVDD
Analog Supply Voltage (+2.7 V to +5.5 V).
NC
No Internal Connection.
DCOM
Digital Common.
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
CLOCK
Clock Input. Data latched on positive edge of clock.
Most Significant Data Bit (MSB).
16
17
18
19
20
21
22
23
24
25
26
27
28
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