參數資料
| 型號： | AD9763ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 17/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL 125MSPS 48LQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC+® |
| 設置時間： | 35ns |
| 位數： | 10 |
| 數據接口： | 并聯 |
| 轉換器數目： | 2 |
| 電壓電源： | 模擬和數字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 125M |
| 產品目錄頁面： | 785 (CN2011-ZH PDF) |
| 配用： | AD9763-EBZ-ND - BOARD EVAL FOR AD9763 |
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AD9763/AD9765/AD9767
Data Sheet
Rev. G | Page 24 of 44
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of 1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the
AD9763/AD9765/AD9767.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. When IOUTFS is decreased
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at IOUTA and IOUTB
does not exceed 0.5 V. Applications requiring the AD9763/
AD9765/AD9767 output (that is, VOUTA and/or VOUTB) to extend its
output compliance range must size RLOAD accordingly. Operation
beyond this compliance range adversely affects the linearity
performance of the AD9763/AD9765/AD9767 and
subsequently degrades its distortion performance.
DIGITAL INPUTS
The digital inputs of the AD9763/AD9765/AD9767 consist of
two independent channels. For the dual-port mode, each DAC has
its own dedicated 10-/12-/14-bit data port: WRT line and CLK line.
In the interleaved timing mode, the function of the digital control
pins changes as described in the Interleaved Mode Timing
section. The 10-/12-/14-bit parallel data inputs follow straight
binary coding, where the most significant bits (MSBs) are DB9P1
and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765,
and DB13P1 and DB13P2 for the AD9767, and the least significant
bits (LSBs) are DB0P1 and DB0P2 for all three parts. IOUTA produces
a full-scale output current when all data bits are at Logic 1. IOUTB
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
DAC TIMING
The AD9763/AD9765/AD9767 can operate in two timing modes,
dual and interleaved, which are described in the following
sections. The block diagram in Figure 61 represents the latch
architecture in the interleaved timing mode.
IQSEL
IQWRT
DAC1
INTERLEAVED
DATA IN, PORT 1
IQCLK
IQRESET
DAC2
÷2
PORT 1
INPUT
LATCH
PORT 2
INPUT
LATCH
DEINTERLEAVED
DATA OUT
DAC1
LATCH
DAC2
LATCH
00
61
7-
0
61
Figure 61. Latch Structure in Interleaved Mode
Dual-Port Mode Timing
When the MODE pin is at Logic 1, the AD9763/AD9765/AD9767
operates in dual-port mode (refer to Figure 57). The AD9763/
AD9765/AD9767 functions as two distinct DACs. Each DAC
has its own completely independent digital input and control lines.
The AD9763/AD9765/AD9767 features a double-buffered data
path. Data enters the device through the channel input latches.
This data is then transferred to the DAC latch in each signal
path. After the data is loaded into the DAC latch, the analog
output settles to its new value.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK must occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns must be
maintained from the rising edge of WRT to the rising edge of CLK.
Timing specifications for dual-port mode are shown in Figure 62
and Figure 63.
DATA IN
WRT1/WRT2
CLK1/CLK2
tPD
IOUTA
OR
IOUTB
tS
tH
tLPW
tCPW
00
61
7-
0
62
Figure 62. Dual-Port Mode Timing
DATA IN
WRT1/WRT2
CLK1/CLK2
XX
D1
D2
D3
D4
IOUTA
OR
IOUTB
D1
D2
D3
D4
D5
00
61
7-
06
3
Figure 63. Dual-Port Mode Timing
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9763ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9763ASTZRL | 功能描述:IC DAC 10BIT DUAL 125MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:TxDAC+® 標準包裝:47 系列:- 設置時間:2µs 位數:14 數據接口:并聯 轉換器數目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD9763-EB | 制造商:Analog Devices 功能描述: |
| AD9763-EBZ | 功能描述:BOARD EVAL FOR AD9763 RoHS:是 類別:編程器，開發(fā)系統 >> 評估板 - 數模轉換器 (DAC) 系列:TxDAC+® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9764 | 制造商:Analog Devices 功能描述: |
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