T
參數(shù)資料
型號： AD9762-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 12/23頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9762
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 125M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時(shí)間： 35ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9762
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
12
Bits
DC ACCURACY
1
Integral Linearity Error (INL)
TA = +25
°C
–2.5
±0.75
+2.5
LSB
TMIN to TMAX
–4.0
±1.0
+4.0
LSB
Differential Nonlinearity (DNL)
TA = +25
°C
–1.5
±0.5
+1.5
LSB
TMIN to TMAX
–2.0
±0.75
+2.0
LSB
ANALOG OUTPUT
Offset Error
–0.025
+0.025
% of FSR
Gain Error (Without Internal Reference)
–10
±2
+10
% of FSR
Gain Error (With Internal Reference)
–10
±1
+10
% of FSR
Full-Scale Output Current2
2.0
20.0
mA
Output Compliance Range
–1.0
+1.25
V
Output Resistance
100
k
Output Capacitance
5
pF
REFERENCE OUTPUT
Reference Voltage
1.08
1.20
1.32
V
Reference Output Current
3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance
1
M
Small Signal Bandwidth (w/o CCOMP1)
4
1.4
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/
°C
Gain Drift (Without Internal Reference)
±50
ppm of FSR/
°C
Gain Drift (With Internal Reference)
±100
ppm of FSR/
°C
Reference Voltage Drift
±50
ppm/
°C
POWER SUPPLY
Supply Voltages
AVDD
5
2.7
5.0
5.5
V
DVDD
2.7
5.0
5.5
V
Analog Supply Current (IAVDD)25
30
mA
Digital Supply Current (IDVDD)
6
1.5
2
mA
Supply Current Sleep Mode (IAVDD)
8.5
mA
Power Dissipation
6 (5 V, I
OUTFS = 20 mA)
133
160
mW
Power Dissipation
7 (5 V, I
OUTFS = 20 mA)
190
mW
Power Dissipation7 (3 V, IOUTFS = 2 mA)
45
mW
Power Supply Rejection Ratio—AVDD
–0.4
+0.4
% of FSR/V
Power Supply Rejection Ratio—DVDD
–0.025
+0.025
% of FSR/V
OPERATING RANGE
–40
+85
°C
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, I
OUTFS, is 32
× the I
REF current.
3Use an external buffer amplifier to drive any external load.
4Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.
5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6Measured at f
CLOCK = 25 MSPS and fOUT = 1.0 MHz.
7Measured as unbuffered voltage output into 50
R
LOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
–2–
REV. B
AD9762–SPECIFICATIONS
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