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參數(shù)資料
| 型號： | AD9761-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 10-Bit TxDAC+⑩ with 2x Interpolation Filters |
| 中文描述： | 雙10位TxDAC系列⑩2倍內(nèi)插濾波器 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 246K |
| 代理商： | AD9761-EB |
AD9761
–10–
REV. A
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9761. The
AD9761 is a complete dual channel, high speed, 10-bit CMOS
DAC capable of operating up to a 40 MHz clock rate. It has
been optimized for the transmit section of wideband communi-
cation systems employing I and Q modulation schemes. Excel-
lent matching characteristics between channels reduces the need
for any external calibration circuitry. Dual matching 2
×
interpo-
lation filters included in the I and Q data path simplify any post,
bandlimiting filter requirements. The AD9761 interfaces with a
single 10-bit digital input bus that supports interleaved I and Q
input data.
ACOM
REFLO
FSADJ
REFIO
"I"
IOUTA
IOUTB
WRITE INPUT
SELECT INPUT
DCOM
DVDD
CLOCK
AD9761
2
3
L"I"
REFERENCE
COMP1
COMP2
COMP3
BIAS
GENERATOR
QOUTA
QOUTB
2
3
L"Q"
CMUX
AVDD
DAC DATA
INPUTS
(10 BITS)
SLEEP
"Q"
Figure 22. Dual DAC Functional Block Diagram
Referring to Figure 22, the AD9761 consists of an analog sec-
tion and a digital section. The analog section includes matched
I and Q 10-bit DACs, a 1.20 V bandgap voltage reference and a
reference control amplifier. The digital section includes: two 2
×
interpolation filters; segment decoding logic; and some addi-
tional digital input interface circuitry. The analog and digital
sections of the AD9761 have separate power supply inputs (i.e.,
AVDD and DVDD) that can operate over a 2.7 V to 5.5 V
range.
Each DAC consists of a large PMOS current source array ca-
pable of providing up to 10 mA of full-scale current, I
OUTFS
.
Each array is divided into 15 equal currents that make up the
four most significant bits (MSBs). The next four bits or middle
bits consist of 15 equal current sources whose value are 1/16th
of an MSB current source. The remaining LSBs are binary
weighted fractions of the middle-bits current sources. All of
these current sources are switched to one or the other of two
output nodes (i.e., IOUTA or IOUTB) via PMOS differential
current switches.
The full-scale output current, I
OUTFS
, of each DAC is regulated
from the same voltage reference and control amplifier, thus
ensuring excellent gain matching and drift characteristics be-
tween DACs. I
OUTFS
can be set from 1 mA to 10 mA via an
external resistor, R
SET
. The external resistor in combination
with both the reference control amplifier and voltage reference,
V
REFIO
, sets the reference current, I
REF
, which is mirrored over
to the segmented current sources with the proper scaling factor.
I
OUTFS
is exactly sixteen times the value of I
REF
.
The I and Q DACs are simultaneously updated on the rising
edge of CLOCK with digital data from their respective 2
×
digi-
tal interpolation filters. The 2
×
interpolation filters essentially
multiplies the input data rate of each DAC by a factor of two,
relative to its original input data rate while simultaneously re-
ducing the magnitude of first image associated with the DAC’s
original input data rate. Since the AD9761 supports a single
10-bit digital bus with interleaved I and Q input data, the origi-
nal I and Q input data rate before interpolation is one-half the
CLOCK rate. After interpolation, the data rate into each I and
Q DAC becomes equal to the CLOCK rate.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to a digital interpolation filter. Images of the
sine wave signal appear around multiples of the DAC’s input
data rate as predicted by the sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modified by the DAC’s sin(x)/(x) response. In many
bandlimited applications, these images must be suppressed by
an analog filter following the DAC. The complexity of this ana-
log filter is typically determined by the proximity of the desired
fundamental to the first image and the required amount of im-
age suppression.
FUNDAMENTAL
1
f
CLOCK
FUNDAMENTALFILTER
SU"OLD"
1
ST
IMAGE
"NEW"
f
CLOCK
1
ST
IMAGE
2
f
CLOCK
f
CLOCK
f
CLOCK
2
f
CLOCK
DACs"SX
TIME DOMAIN
FREQUENCY DOMAIN
2x INTERPOLATION FILTER
INPUT DATA LATCH
DAC
f
CLOCK
f
CLOCK
2
f
CLOCK
2
f
CLOCK
2
2x
Figure 23. Time and Frequency Domain Example of Digital Interpolation Filter
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|---|---|
| AD9761-EBZ | 功能描述:BOARD EVAL FOR AD9761 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9762 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table |
| AD9762AR | 功能描述:IC DAC 12BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9762ARRL | 功能描述:IC DAC 12BIT 100KSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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