參數(shù)資料
型號： AD9760AR50
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 10-Bit, 125 MSPS TxDAC D/A Converter
中文描述： PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
封裝： 0.300 INCH, SOIC-28
文件頁數(shù)： 2/23頁
文件大小： 412K
代理商： AD9760AR50
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
MONOTONICITY
ANALOG OUTPUT
Offset Error
Gain Error
(Without Internal Reference)
Gain Error
(With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
10
Bits
–1.0
–0.5
Guaranteed Over Specified Temperature Range
±
0.5
±
0.25
+1.0
+0.5
LSB
LSB
–0.025
–10
–10
2.0
–1.0
+0.025
+10
+10
20.0
1.25
% of FSR
% of FSR
% of FSR
mA
V
k
pF
±
2
±
1
100
5
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
1.08
1.20
100
1.32
V
nA
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o C
COMP1
)
4
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift
(Without Internal Reference)
Gain Drift
(With Internal Reference)
Reference Voltage Drift
0.1
1.25
V
M
MHz
1
1.4
0
±
50
±
100
±
50
ppm of FSR/
°
C
ppm of FSR/
°
C
ppm of FSR/
°
C
ppm/
°
C
POWER SUPPLY
Supply Voltages
AVDD
5
DVDD
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
6
Supply Current Sleep Mode (I
AVDD
)
Power Dissipation
6
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(3 V, I
OUTFS
= 2 mA)
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
2.7
2.7
5.0
5.0
25
3
5.5
5.5
30
5
8.5
175
V
V
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°
C
140
190
45
–0.04
–0.025
+0.04
+0.025
OPERATING RANGE
–40
+85
NOTES
1
Measured at I
OUTA
, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32
×
the I
REF
current.
3
Use an external buffer amplifier to drive any external load.
4
Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.
5
For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6
Measured at f
CLOCK
= 50 MSPS and f
OUT
= 1.0 MHz.
7
Measured as unbuffered voltage output into 50
R
LOAD
at I
OUTA
and I
OUTB
, f
CLOCK
= 100 MSPS and f
OUT
= 40 MHz.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
–2–
REV. B
AD9760/AD9760-50–SPECIFICATIONS
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