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參數(shù)資料
| 型號： | AD9760* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator; Package: DFN; No of Pins: 16; Temperature Range: -40°C to +125°C |
| 中文描述： | 10位。 125 MSPS的TxDAC系列D / A轉換 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 412K |
AD9760
–
11
–
REV. B
FUNCTIONAL DESCRIPTION
Figure 39 shows a simplified block diagram of the AD9760.
The AD9760 consists of a large PMOS current source array that
is capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the 5 most sig-
nificant bits (MSBs). The next 4 bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs is a binary weighted frac-
tion of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 k
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., I
OUTA
or I
OUTB
) via PMOS differen-
tial current switches. The switches are based on a new architec-
ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif-
ferential current switches.
The analog and digital sections of the AD9760 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R
SET
. The external resistor, in combination with
both the reference control amplifier and voltage reference
V
REFIO
, sets the reference current I
REF
, which is mirrored over to
the segmented current sources with the proper scaling factor.
The full-scale current, I
OUTFS
, is thirty-two times the value of I
REF
.
DAC TRANSFER FUNCTION
The AD9760 provides complementary current outputs, I
OUTA
and I
OUTB
. I
OUTA
will provide a near full-scale current output,
I
OUTFS
, when all bits are high (i.e., DAC CODE = 1023) while
I
OUTB
, the complementary output, provides no current. The
current output appearing at I
OUTA
and I
OUTB
is a function of
both the input code and I
OUTFS
and can be expressed as:
I
OUTA
= (
DAC CODE
/1024)
×
I
OUTFS
I
OUTB
= (1023 –
DAC CODE
)/1024
×
I
OUTFS
where
DAC CODE
= 0 to 1023 (i.e., Decimal Representation).
As mentioned previously, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage,
V
REFIO
and external resistor R
SET
. It can be expressed as:
I
OUTFS
= 32
×
I
REF
where
I
REF
=
V
REFIO
/
R
SET
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, I
OUTA
and I
OUTB
should be directly connected to matching resistive
loads, R
LOAD
, that are tied to analog common, ACOM. Note,
R
LOAD
may represent the equivalent load resistance seen by
I
OUTA
or I
OUTB
as would be the case in a doubly terminated
50
or 75
cable. The single-ended voltage output appearing
at the I
OUTA
and I
OUTB
nodes is simply:
V
OUTA
=
I
OUTA
×
R
LOAD
V
OUTB
=
I
OUTB
×
R
LOAD
Note the full-scale value of V
OUTA
and V
OUTB
should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
(1)
(2)
(3)
(4)
(5)
(6)
DIGITAL DATA INPUTS (DB9
–
DB0)
50pF
COMP1
+1.20V REF
AVDD
ACOM
REFLO
COMP2
PMOS
CURRENT SOURCE
ARRAY
0.1 F
+5V
SEGMENTED SWITCHES
FOR DB9
–
DB1
LSB
SWITCH
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
2k
0.1 F
I
OUTA
I
OUTB
0.1 F
AD9760
SLEEP
LATCHES
I
REF
V
REFIO
CLOCK
I
OUTB
I
OUTA
R
LOAD
50
V
OUTB
V
OUTA
R
LOAD
50
V
DIFF
= V
OUTA
–
V
OUTB
Figure 39. Functional Block Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9760-50AR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
| AD9760AR | 功能描述:IC DAC 10BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD9760AR50 | 功能描述:IC DAC 10BIT 50MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD9760AR50RL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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