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參數(shù)資料
| 型號： | AD9751 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit,300 MSPS High Speed T×DAC+TM D/A Converter(300MSPS,超高速,單通道10位D/A轉(zhuǎn)換器) |
| 中文描述： | 10位，300 MSPS的高速厚×援商標D / A轉(zhuǎn)換（300MSPS，超高速，單通道10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 156K |
| 代理商： | AD9751 |
11 REV. PrA
DATA
itself as phase noise on a reconstructed waveform.
T hus, the clock input should be driven by the fastest
logic family suitable for the application.
Note that the clock input could also be driven via a
sine wave, which is centered around the digital thresh-
old (i.e., DVDD/2) and meets the min/max logic
threshold. T his will typically result in a slight degrada-
tion in the phase noise, which becomes more notice-
able at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of
the digital logic threshold should be considered since
it will affect the effective clock duty cycle and, subse-
quently, cut into the required data setup and hold
times.
TECHNCAL
T he AD9751 features a flexible differential clock input
operatingfrom separate supplies (i.e., C L K VDD,
CL K COM) to achieve optimum jitter performance.
T he two clock inputs, CLK + and CLK -, can be driven
from a single-ended or differential clock source. For
single ended operation, CLK + should be driven by a
logic source while CLK - should be set to the threshold
voltage of the logic source. T his can be done via a
resistor divider/capacitor network as shown in Figure
12a. For differential operation, both CLK + and CLK -
should be biased to CLK VDD/2 via a resistor divider
network as shown in Figure 12b.
Since the output of the AD9751 is capable of being
updated at up to 300 MSPS, the quality of the clock
and data input signals are important in achieving the
optimum performance. Operating the AD9751 with
reduced logic swings and a corresponding digital
supply (DVDD) will result in the lowest data
feedthrough and on-chip digital noise. T he drivers of
the digital data interface circuitry should be specified
to meet the minimum setup and hold times of the
AD9751 as well as its required min/max input logic
level thresholds.
Digital signal paths should be kept short and run
lengths matched to avoid propagation delay mismatch.
T he insertion of a low value resistor network (i.e., 20
to 100
) between the AD9751 digital inputs and
driver outputs may be helpful in reducing any over-
shooting and ringing at the digital inputs that contrib-
ute to data feedthrough. For longer run lengths and
high data update rates, strip line techniques with
proper termination resistors should be considered to
maintain “clean” digital inputs.
T he external clock driver circuitry should provide the
AD9751 with a low jitter clock input meeting the min/
max logic levels while providing fast edges. Fast clock
edges will help minimize any jitter that will manifest
Figure 12a. Single Ended Clock Interface
0.1
μ
F
V
T hreshold
CLK +
CLK VDD
CLK -
CLK COM
R
SERIES
0.1
μ
F
CLK +
CLK VDD
CLK -
CLK COM
0.1
μ
F
0.1
μ
F
Figure 12b. Differential Clock Interface
AD9751
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9751AST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC |
| AD9751ASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:10-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Tape and Reel |
| AD9751ASTZ | 功能描述:IC DAC 10BIT 300MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9751ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9751ASTZRL | 功能描述:IC DAC 10BIT 300MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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