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參數(shù)資料
| 型號(hào)： | AD974BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 202K |
| 代理商： | AD974BR |
REV. A
AD974
–5–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
2–5, 25–28
6
7
AGND1
VxA, VxB
BIP
CAP
Analog Ground. Used as the ground reference point for the REF pin.
Analog Input. Refer to Table I for input range configuration.
Bipolar Offset. Connect VxA inputs to provide Bipolar input range.
Reference Buffer Output. Connect a 2.2
μ
F tantalum capacitor between CAP and Analog
Ground.
Reference Input/Output. The internal +2.5 V reference is available at this pin. Alternatively an
external reference can be used to override the internal reference. In either case, connect a 2.2
μ
F
tantalum capacitor between REF and Analog Ground.
Analog Ground.
Read/
Convert
Input. Used to control the conversion and read modes. With
CS
LOW, a falling
edge on R/
C
holds the analog input signal internally and starts a conversion; a rising edge enables
the transmission of the conversion result.
Digital Power Supply. Nominally +5 V.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited. The conversion result from the previous conversion is stored in the onboard shift
register.
Digital select input for choosing the internal or an external data clock. With EXT/
INT
tied LOW,
after initiating a conversion, 16 DATACLK pulses transmit the previous conversion result as
shown in Figure 3. With EXT/
INT
set to a Logic HIGH, output data is synchronized to an
external clock signal connected to the DATACLK input. Data is output as indicated in Figure 4
through Figure 9.
Digital Ground.
Digital output frame synchronization for use with an external data clock (EXT/
INT
= Logic
HIGH). When a read sequence is initiated, a pulse one DATACLK period wide is output
synchronous to the external data clock.
Serial data clock input or output, dependent upon the logic state of the EXT/
INT
pin. When
using the internal data clock (EXT/
INT
= Logic LOW), a conversion start sequence will initiate
transmission of 16 DATACLK periods. Output data is synchronous to this clock and is valid on
both its rising and falling edges (Figure 3). When using an external data clock (EXT/
INT
= Logic
HIGH), the
CS
and R/
C
signals control how conversion data is accessed.
The serial data output is synchronized to DATACLK. Conversion results are stored in an on-
chip register. The AD974 provides the conversion result, MSB first, from its internal shift regis-
ter. When using the internal data clock (EXT/
INT
= Logic LOW), DATA is valid on both the
rising and falling edges of DATACLK. Using an external data clock (EXT/
INT
= Logic HIGH)
allows previous conversion data to be accessed during a conversion (Figures 5, 7 and 9) or the
conversion result can be accessed after the completion of a conversion (Figures 4, 6 and 8).
Multiplexer Write Inputs. These inputs are internally ORed to generate the mux latch inputs.
The latch is transparent when
WR1
and
WR2
are tied low.
Chip Select Input. With R/
C
LOW, a falling edge on
CS
will initiate a conversion. With R/
C
HIGH, a falling edge on
CS
will enable the serial data output sequence.
Busy Output. Goes LOW when a conversion is started, and remains LOW until the conversion is
completed and the data is latched into the on-chip shift register.
Address multiplexer inputs latched with the
WR1
,
WR2
inputs.
8
REF
9
10
AGND2
R/
C
11
12
V
DIG
PWRD
13
EXT/
INT
14
15
DGND
SYNC
16
DATACLK
17
DATA
18, 19
WR1
,
WR2
20
CS
21
BUSY
22, 23
A1, A0
A1
A0
Data Available from Channel
0
0
1
1
0
1
0
1
AIN 1
AIN 2
AIN 3
AIN 4
24
V
ANA
Analog Power Supply. Nominally +5 V.
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