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    參數(shù)資料
    型號(hào): AD974AN
    廠商: Analog Devices Inc
    文件頁(yè)數(shù): 14/20頁(yè)
    文件大小: 0K
    描述: IC DAS 16BIT 4CH 200KSPS 28-DIP
    標(biāo)準(zhǔn)包裝: 13
    類(lèi)型: 數(shù)據(jù)采集系統(tǒng)(DAS)
    分辨率(位): 16 b
    采樣率(每秒): 200k
    數(shù)據(jù)接口: 串行
    電壓電源: 模擬和數(shù)字
    電源電壓: 4.75 V ~ 5.25 V
    工作溫度: -40°C ~ 85°C
    安裝類(lèi)型: 通孔
    封裝/外殼: 28-DIP(0.600",15.24mm)
    供應(yīng)商設(shè)備封裝: 28-PDIP
    包裝: 管件
    配用: EVAL-AD974CB-ND - BOARD EVAL FOR AD974
    REV. A
    –3–
    AD974
    A Grade
    B Grade
    Parameter
    Conditions
    Min
    Typ
    Max
    Min
    Typ
    Max
    Units
    DIGITAL OUTPUTS
    Data Format
    Serial 16 Bits
    Data Coding
    Straight Binary
    VOL
    ISINK = 1.6 mA
    +0.4
    V
    VOH
    ISOURCE = 500
    A+4
    +4
    V
    Output Capacitance
    High-Z State
    15
    pF
    Leakage Current
    High-Z State
    VOUT = 0 V to VDIG
    ±5
    A
    POWER SUPPLIES
    Specified Performance
    VDIG
    +4.75
    +5
    +5.25
    +4.75 +5
    +5.25
    V
    VANA
    +4.75
    +5
    +5.25
    +4.75 +5
    +5.25
    V
    IDIG
    4.5
    mA
    IANA
    14
    mA
    Power Dissipation
    PWRD LOW
    120
    mW
    PWRD HIGH
    50
    W
    TEMPERATURE RANGE
    Specified Performance
    TMIN to TMAX
    –40
    +85
    –40
    +85
    °C
    NOTES
    1LSB means Least Significant Bit. With a
    ±10 V input, one LSB is 305 V.
    2Typical rms noise at worst case transitions and temperatures.
    3Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect
    of offset error. For bipolar input, the Full-Scale Error is the worst case of either the –Full-Scale or +Full-Scale code transition voltage errors. For unipolar input
    ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.
    4External 2.5 V reference connected to REF.
    5All specifications in dB are referred to a full-scale
    ±10 V input.
    6Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy.
    7Recovers to specified performance after a 2
    × FS input overvoltage.
    Specifications subject to change without notice.
    TIMING SPECIFICATIONS
    Parameter
    Symbol
    Min
    Typ
    Max
    Units
    Convert Pulsewidth
    t1
    50
    ns
    R/
    C, CS to BUSY Delay
    t2
    100
    ns
    BUSY LOW Time
    t3
    4.0
    s
    BUSY Delay after End of Conversion
    t4
    50
    ns
    Aperture Delay
    t5
    40
    ns
    Conversion Time
    t6
    3.8
    4.0
    s
    Acquisition Time
    t7
    1.0
    s
    Throughput Time
    t6 + t7
    5
    s
    R/
    C Low to DATACLK Delay
    t8
    220
    ns
    DATACLK Period
    t9
    220
    ns
    DATA Valid Setup Time
    t10
    50
    ns
    DATA Valid Hold Time
    t11
    20
    ns
    EXT. DATACLK Period
    t12
    66
    ns
    EXT. DATACLK HIGH
    t13
    20
    ns
    EXT. DATACLK LOW
    t14
    30
    ns
    R/
    C, CS to EXT. DATACLK Setup Time
    t15
    20
    t12 + 5
    ns
    R/
    C to CS Setup Time
    t16
    10
    ns
    EXT. DATACLK to SYNC Delay
    t17
    15
    66
    ns
    EXT. DATACLK to DATA Valid Delay
    t18
    25
    66
    ns
    CS to EXT. DATACLK Rising Edge Delay
    t19
    10
    ns
    Previous DATA Valid after
    CS, R/C Low
    t20
    3.5
    s
    BUSY to EXT. DATACLK Setup Time
    t21
    5ns
    Final EXT. DATACLK to
    BUSY Rising Edge
    t22
    1.7
    s
    A0, A1 to
    WR1, WR2 Setup Time
    t23
    10
    ns
    A0, A1 to
    WR1, WR2 Hold Time
    t24
    10
    ns
    WR1, WR2 Pulsewidth
    t25
    50
    ns
    Specifications subject to change without notic e.
    (fS = 200 kHz, VDIG = VANA = +5 V, –40 C to +85 C)
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