參數(shù)資料
型號(hào)： AD9744ARU
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 14-Bit, 165 MSPS TxDAC D/A Converter
中文描述： PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PDSO28
封裝： MO-153AE, TSSOP-28
文件頁數(shù)： 10/28頁
文件大小： 1142K
代理商： AD9744ARU
REV. A
–10–
AD9744
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9744. The
AD9744 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I
OUTFS
). The array is divided into 31 equal currents
that make up the five most significant bits (MSBs). The next
four bits, or middle bits, consist of 15 equal current sources
whose value is 1/16th of an MSB current source. The remaining
LSBs are binary weighted fractions of the middle bits current
sources. Implementing the middle and lower bits with current
sources, instead of an R-2R ladder, enhances its dynamic per-
formance for multitone or low amplitude signals and helps
maintain the DAC’s high output impedance (i.e., >100 k
W
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces vari-
ous timing errors and provides matching complementary drive
signals to the inputs of the differential current switches.
The analog and digital sections of the AD9744 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 165 MSPS, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the asso-
ciated differential switches, a 1.2 V band gap voltage reference,
and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R
SET
, connected to the full-scale adjust (FS ADJ)
pin. The external resistor, in combination with both the refer-
ence control amplifier and voltage reference V
REFIO
, sets the
reference current I
REF
, which is replicated to the segmented
current sources with the proper scaling factor. The full-scale
current, I
OUTFS
, is 32 times I
REF
.
DIGITAL DATA INPUTS (DB13–DB0)
150pF
+1.2V REF
AVDD
ACOM
REFLO
PMOS
CURRENT SOURCE
ARRAY
3.3V
SEGMENTED SWITCHES
FOR DB13–DB5
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
3.3V
R
SET
2k
0.1 F
IOUTA
IOUTB
AD9744
SLEEP
LATCHES
I
REF
V
REFIO
CLOCK
IOUTB
IOUTA
R
LOAD
50
V
OUTB
V
OUTA
R
LOAD
50
V
DIFF
= V
OUTA
– V
OUTB
MODE
Figure 3. Simplified Block Diagram (SOIC/TSSOP Packages)
REFERENCE OPERATION
The AD9744 contains an internal 1.2 V band gap reference. The
internal reference can be disabled by raising REFLO to AVDD.
It can also be easily overridden by an external reference with no
effect on performance. REFIO serves as either an input or an
output depending on whether the internal or an external reference
is used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1
m
F capacitor and connect REFLO to
ACOM via a resistance less than 5
W
. The internal reference volt-
age will be present at REFIO. If the voltage at REFIO is to be
used anywhere else in the circuit, an external buffer amplifier with
an input bias current of less than 100 nA should be used. An
example of the use of the internal reference is shown in Figure 4.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
2k
0.1 F
AD9744
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
Figure 4. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in
Figure 5. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1
m
F
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
R
SET
AD9744
EXTERNAL
REF
I
REF
=
V
REFIO
/R
SET
AVDD
REFERENCE
CONTROL
AMPLIFIER
V
REFIO
Figure 5. External Reference Configuration
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