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參數(shù)資料
| 型號： | AD9744AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 165 MSPS TxDAC D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PDSO28 |
| 封裝： | 0.300 INCH, MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 1142K |
| 代理商： | AD9744AR |
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REV. A
–12–
AD9744
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9744.
The positive output compliance range is slightly dependent on the
full-scale output current, I
OUTFS
. It degrades slightly from its
nominal 1.2 V for an I
OUTFS
= 20 mA to 1 V for an I
OUTFS
=
2 mA. The optimum distortion performance for a single-
ended or differential output is achieved when the maximum
full-scale signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9744 digital section consists of 14 input bit channels
and a clock input. The 14-bit parallel data inputs follow stan-
dard positive binary coding, where DB13 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
DVDD
DIGITAL
INPUT
Figure 6. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
165 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock qual-
ity, and jitter is a key concern. Any noise or jitter in the clock
will translate directly into the DAC output. Optimal perfor-
mance will be achieved if the CLOCK input has a sharp rising
edge, since the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes. The
mode selection is controlled by the CMODE input, as summa-
rized in Table I. Connecting CMODE to CLKCOM selects the
single-ended clock input. In this mode, the CLK+ input is driven
with rail-to-rail swings and the CLK– input is left floating. If
CMODE is connected to CLKVDD, the differential receiver
mode is selected. In this mode, both inputs are high impedance.
The final mode is selected by floating CMODE. This mode is
also differential, but internal terminations for positive emitter-
coupled logic (PECL) are activated. There is no significant
performance difference among any of the three clock input modes.
Table I. Clock Mode Selection
CMODE Pin
Clock Input Mode
CLKCOM
CLKVDD
Float
Single-Ended
Differential
PECL
The single-ended input mode operates in the same way as the
CLOCK input in the 28-lead packages, as described previously.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK– inputs can vary from 0.75 V to 2.25 V,
and the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 7. These termination resistors are untrimmed and can
vary up to
±
20%. However, matching between the resistors
should generally be better than
±
1%
CLK+
TO DAC CORE
CLK–
V
TT
= 1.3V NOM
50
50
AD9744
CLOCK
RECEIVER
Figure 7. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relation-
ship between the position of the clock edges and the time at
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9744ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH 14-bit 28-Pin SOIC W T/R |
| AD9744ARU | 功能描述:IC DAC 14BIT 210MSPS 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9744ARURL7 | 功能描述:IC DAC 14BIT 210MSPS 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD9744ARUZ | 功能描述:IC DAC 14BIT 210MSPS 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9744ARUZ | 制造商:Analog Devices 功能描述:D/A CONVERTER (D-A) IC 制造商:Analog Devices 功能描述:IC, DAC, 14BIT, 210MSPS, TSSOP-28 |
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