參數(shù)資料
型號(hào)： AD9744ACPRL7
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： 14-Bit, 165 MSPS TxDAC D/A Converter
中文描述： PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, QCC32
封裝： MO-220-VHHD-2, LFCSP-32
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 1142K
代理商： AD9744ACPRL7
REV. A
AD9744
–7–
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25
∞
C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per
∞
C. For reference drift, the drift is reported in
ppm per
∞
C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic compo-
nents to the rms value of the measured input signal. It is expressed
as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference between
the rms amplitude of a carrier tone to the peak spurious signal
in the region of a removed tone.
150pF
+1.2V REF
AVDD
ACOM
REFLO
PMOS
CURRENT SOURCE
ARRAY
SEGMENTED SWITCHES
FOR DB13–DB5
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
3.3V
R
SET
2k
0.1 F
DVDD
DCOM
IOUTA
IOUTB
AD9744
SLEEP
50
RETIMED
CLOCK
OUTPUT
*
LATCHES
DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50
50
RHODE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
MINI-CIRCUITS
T1-1T
*
AWG2021 CLOCK RETIMED
SO THAT THE DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
3.3V
MODE
Figure 2. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages)
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