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參數(shù)資料
| 型號： | AD9744ACP-PCB |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 165 MSPS TxDAC D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 1142K |
| 代理商： | AD9744ACP-PCB |
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REV. A
AD9744
–13–
which the input data changes. The AD9744 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when apply-
ing the AD9744 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 8 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement, while
at higher rates, more care must be taken.
–3
–2
2
–1
0
1
65
75
ns
3
55
45
35
60
70
50
40
50MHz SFDR
20MHz SFDR
50MHz SFDR
Figure 8. SFDR vs. Clock Placement @ f
OUT
= 20 MHz
and 50 MHz
Sleep Mode Operation
The AD9744 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and tempera-
ture range. This mode can be activated by applying a logic level
1 to the SLEEP pin. The SLEEP pin logic threshold is equal to
0.5
￥
AVDD. This digital input also contains an active pull-
down circuit that ensures that the AD9744 remains enabled if
this input is left disconnected. The AD9744 takes less than
50 ns to power down and approximately 5
m
s to power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9744 is dependent on
several factors that include:
∑
The power supply voltages (AVDD, CLKVDD, and DVDD)
∑
The full-scale current output I
OUTFS
∑
The update rate f
CLOCK
∑
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, I
AVDD
, and the digital supply current, I
DVDD
.
I
AVDD
is directly proportional to I
OUTFS
, as shown in Figure 9,
and is insensitive to f
CLOCK
. Conversely, I
DVDD
is dependent on
both the digital input waveform, f
CLOCK
, and digital supply
DVDD. Figure 10 shows I
DVDD
as a function of full-scale sine
wave output ratios (f
OUT
/f
CLOCK
) for various update rates with
DVDD = 3.3 V.
I
OUTFS
(mA)
35
0
2
I
A
30
25
20
15
10
4
6
8
10
12
14
16
18
20
Figure 9. I
AVDD
vs. I
OUTFS
RATIO (
f
OUT
/
f
CLOCK
)
16
0.01
1
0.1
I
D
14
12
10
8
6
4
2
0
165MSPS
125MSPS
65MSPS
Figure 10. I
DVDD
vs. Ratio @ DVDD = 3.3 V
50
100
150
0
1
2
3
4
5
6
7
8
9
10
f
CLOCK
(MSPS)
I
C
m
200
0
DIFF
PECL
SE
Figure 11. I
CLKVDD
vs. f
CLOCK
and Clock Mode
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