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參數(shù)資料
| 型號： | AD9744-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 165 MSPS TxDAC D/A Converter |
| 中文描述： | 14位，165 MSPS的TxDAC系列D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 1142K |
| 代理商： | AD9744-EB |
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REV. A
AD9744
–15–
values of I
OUTFS
and R
LOAD
can be selected as long as the positive
compliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL), discussed in the
Analog Output section. For optimum INL performance, the
single-ended, buffered voltage output configuration is suggested.
AD9744
IOUTA
IOUTB
21
50
25
50
V
OUTA
= 0V TO 0.5V
I
OUTFS
= 20mA
22
Figure 15. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 16 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9744
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, minimizing the nonlinear output impedance effect on
the DAC’s INL performance as described in the Analog Output
section. Although this single-ended configuration typically provides
the best dc linearity performance, its ac distortion performance
at higher DAC update rates may be limited by U1’s slew rate
capabilities. U1 provides a negative unipolar output voltage, and
its full-scale output voltage is simply the product of R
FB
and
I
OUTFS
. The full-scale output should be set within U1’s voltage
output swing capabilities by scaling I
OUTFS
and/or R
FB
. An
improvement in ac distortion performance may result with a
reduced I
OUTFS
since the signal current U1 will be required to
sink less signal current.
AD9744
22
IOUTA
IOUTB
21
C
OPT
200
U1
V
OUT
= I
OUTFS
R
FB
I
OUTFS
= 10mA
R
FB
200
Figure 16. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit board
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum per-
formance. Figures 21 to 24 illustrate the recommended printed
circuit board ground, power, and signal plane layouts implemented
on the AD9744 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated
with the DAC’s full-scale current, I
OUTFS
. AC noise on the dc
supplies is common in applications where the power distribution
is generated by a switching power supply. Typically, switching
power supply noise will occur over the spectrum from tens of
kHz to several MHz. The PSRR versus frequency of the AD9744
AVDD supply over this frequency range is shown in Figure 17.
FREQUENCY (MHz)
85
40
12
6
0
P
80
75
70
65
60
55
50
2
4
8
10
45
Figure 17. Power Supply Rejection Ratio (PSRR)
Note that the ratio in Figure 17 is calculated as amps out/volts in.
Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative different size
of these switches, the PSRR is very code dependent. This can
produce a mixing effect that can modulate low frequency power
supply noise to higher frequencies. Worst-case PSRR for either
one of the differential DAC outputs will occur when the full-scale
current is directed toward that output. As a result, the PSRR
measurement in Figure 17 represents a worst-case condition in
which the digital inputs remain static and the full-scale output
current of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switch-
ing frequency of 250 kHz produces 10 mV of noise and, for
simplicity’s sake (ignoring harmonics), all of this noise is con-
centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise superimposed on the DAC’s
full-scale current, I
OUTFS
, one must determine the PSRR in dB
using Figure 17 at 250 kHz. To calculate the PSRR for a given
R
LOAD
, such that the units of PSRR are converted from A/V to
V/V, adjust the curve in Figure 17 by the scaling factor 20
￥
log
(R
LOAD
). For instance, if R
LOAD
is 50
W
, the PSRR is reduced by
34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 17, becomes 51 dB V
OUT
/V
IN
).
Proper grounding and decoupling should be a primary objec-
tive in any high speed, high resolution system. The AD9744
features separate analog and digital supplies and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, AVDD, the analog supply, should be
decoupled to ACOM, the analog common, as close to the chip
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