參數(shù)資料
型號： AD9743BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 14/28頁
文件大?。?/td> 0K
描述： IC DAC DUAL 10B 250MSPS 72-LFCSP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 2,000
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 345mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 250M
Data Sheet
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 21 of 28
SPI REGISTER DESCRIPTIONS
Table 15.
Register
Address
Bit
Name
Description
SPI Control
0x00
7
SDIODIR
0, operate SPI in 4-wire mode, SDIO pin operates as an input only
1, operate SPI in 3-wire mode, SDIO pin operates as a bidirectional I/O line
6
LSBFIRST
0, LSBFIRST off, SPI serial data mode is MSB to LSB
1, LSBFIRST on, SPI serial data mode is LSB to MSB
5
SWRESET
0, resume normal operation following software RESET
1, software RESET; loads default values to all registers (except Register 0x00)
Data Control
0x02
7
DATTYPE
0, DAC input data is twos complement binary format
1, DAC input data is unsigned binary format
6
ONEPORT
0, normal two port input mode
1, optional single port input mode, interleaved data received on Port 1 only
4
INVDCO
1, inverts data clock output signal
Power Down
0x03
7
PD_DCO
1, power down data clock output
5
PD_AUX2
1, power down AUX2 DAC
4
PD_AUX1
1, power down AUX1 DAC
3
PD_BIAS
1, power down reference voltage bias circuit
2
PD_CLK
1, power down DAC clock input circuit
1
PD_DAC2
1, power down DAC2 analog output
0
PD_DAC1
1, power down DAC1 analog output
DAC Mode Select
0x0A
3:2
DAC1MOD<1:0>
00, selects normal mode, DAC1
01, selects mix mode, DAC1
10, selects return-to-zero mode, DAC1
1:0
DAC2MOD<1:0>
00, selects normal mode, DAC2
01, selects mix mode, DAC2
10, selects return-to-zero mode, DAC2
DAC1 Gain
0x0B
7:0
DAC1FSC<7:0>
DAC1 full-scale 10-bit adjustment word
0x0C
1:0
DAC1FSC<9:8>
0x03FF, sets full-scale current to the maximum value of 31.66 mA
0x01F9, sets full-scale current to the nominal value of 20.0 mA
0x0000, sets full-scale current to the minimum value of 8.64 mA
AUX DAC1
0x0D
7:0
AUXDAC1<7:0>
Auxiliary DAC1 10-bit output current adjustment word
0x0E
1:0
AUXDAC1<9:8>
0x03FF, sets output current magnitude to 2.0 mA
0x0200, sets output current magnitude to 1.0 mA
0x0000, sets output current magnitude to 0.0 mA
7
AUX1PIN
1, AUX1P output pin is active
0, AUX1N output pin is active
6
AUX1DIR
0, configures AUX1 DAC output to source current
1, configures AUX1 DAC output to sink current
DAC2 Gain
0x0F
7:0
DAC2FSC<7:0>
DAC2 full-scale 10-bit adjustment word
0x10
1:0
DAC2FSC<9:8>
0x03FF, sets full-scale current to the maximum value of 31.66 mA
0x01F9, sets full-scale current to the nominal value of 20.0 mA
0x0000, sets full-scale current to the minimum value of 8.64 mA
AUX DAC2
0x11
7:0
AUXDAC2<7:0>
Auxiliary DAC2 10-bit output current adjustment word
0x12
1:0
AUXDAC2<9:8>
0x03FF, sets output current magnitude to 2.0 mA
0x0200, sets output current to 1.0 mA
0x0000, sets output current to 0.0 mA
7
AUX2PIN
1, AUX2P output pin is active
0, AUX2N output pin is active
6
AUX2DIR
0, configures AUX2 DAC output to source current
1, configures AUX2 DAC output to sink current
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參數(shù)描述
AD9743-DPG2-EBZ 功能描述:IC DAC DUAL 10BIT 72LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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