參數(shù)資料
型號： AD9742ACP-PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 10/32頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9742ACP
產(chǎn)品培訓模塊： DAC Architectures
標準包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 210M
數(shù)據(jù)接口： 并聯(lián)
設置時間： 11ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9742
相關產(chǎn)品： AD9742ARZ-ND - IC DAC 12BIT 210MSPS 28-SOIC
AD9742ACPZ-ND - IC DAC 12BIT 210MSPS 32LFCSP
AD9742ACPZRL7-ND - IC DAC 12BIT 210MSPS 32-LFCSP
AD9742ARZRL-ND - IC DAC 12BIT 210MSPS 28-SOIC
AD9742ARUZRL7-ND - IC DAC 12BIT 210MSPS 28-TSSOP
AD9742ARUZ-ND - IC DAC 12BIT 210MSPS 28-TSSOP
AD9742ARURL7-ND - IC DAC 12BIT 210MSPS 28-TSSOP
AD9742AR-ND - IC DAC 12BIT 210MSPS 28-SOIC
AD9742ARU-ND - IC DAC 12BIT 210MSPS 28-TSSOP
AD9742
Data Sheet
Rev. C | Page 18 of 32
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake (ignoring harmonics), all of this noise is concentrated at
250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC’s full-scale
current, IOUTFS, one must determine the PSRR in dB using Figure 36
at 250 kHz. To calculate the PSRR for a given RLOAD, such that the
units of PSRR are converted from A/V to V/V, adjust the curve in
Figure 36 by the scaling factor 20 log (RLOAD). For instance, if
RLOAD is 50 , the PSRR is reduced by 34 dB (i.e., PSRR of the DAC
at 250 kHz, which is 85 dB in Figure 36, becomes 51 dB VOUT/VIN).
Proper grounding and decoupling should be a primary objective in
any high speed, high resolution system. The AD9742 features
separate analog and digital supplies and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physically
possible. Similarly, DVDD, the digital supply, should be decoupled
to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 37. The circuit consists
of a differential LC filter with separate power supply and return
lines. Lower noise can be attained by using low ESR type
electrolytic and tantalum capacitors.
100
F
ELECT.
0.1
F
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
10
F–22F
TANT.
02912-B-036
Figure 37. Differential LC Filter for Single 3.3 V Applications
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AD9742AR 功能描述:IC DAC 12BIT 210MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
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