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參數(shù)資料
| 型號(hào)： | AD9742-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 165 MSPS TxDAC D/A Converter |
| 中文描述： | 12位，165 MSPS的TxDAC系列D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大?。?/td> | 783K |
| 代理商： | AD9742-EB |
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REV. 0
–4–
AD9742
DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
2.1
3
0
V
V
m
A
m
A
pF
ns
ns
ns
0.9
+10
+10
–10
–10
5
2.0
1.5
1.5
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9742 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options
*
Model
AD9742AR
AD9742ARU –40
∞
C to +85
∞
C 28-Lead TSSOP
AD9742-EB
–40
∞
C to +85
∞
C 28-Lead 300 Mil SOIC R-28
RU-28
Evaluation Board
*
R = Small Outline IC; RU = Thin Shrink Small Outline Package
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300-Mil SOIC
= 71.4
∞
C/W
28-Lead TSSOP
JA
= 97.9
∞
C/W
ABSOLUTE MAXIMUM RATINGS
*
With
Respect to
Parameter
Min
Max
Unit
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
REFIO, REFLO, FSADJ
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
–0.3
–0.3
–0.3
–3.9
–0.3
–0.3
–1.0
–0.3
+3.9
+3.9
+0.3
+3.9
DVDD + 0.3 V
DVDD + 0.3 V
AVDD + 0.3
AVDD + 0.3
150
+150
300
V
V
V
V
V
V
∞
C
∞
C
∞
C
–65
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
0.1%
0.1%
t
S
t
H
t
LPW
t
PD
t
ST
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9742AR | 12-Bit, 165 MSPS TxDAC D/A Converter |
| AD9742ARU | 12-Bit, 165 MSPS TxDAC D/A Converter |
| AD9744ARURL7 | 14-Bit, 165 MSPS TxDAC D/A Converter |
| AD9744 | 14-Bit, 165 MSPS TxDAC D/A Converter |
| AD9744-EB | 14-Bit, 165 MSPS TxDAC D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
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