參數(shù)資料
型號(hào): AD9740ARU
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 10-Bit, 165 MSPS TxDAC D/A Converter
中文描述: PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 10-BIT DAC, PDSO28
封裝: MO-153AE, TSSOP-28
文件頁(yè)數(shù): 5/20頁(yè)
文件大小: 743K
代理商: AD9740ARU
REV. 0
AD9740
–5–
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9740
NC = NO CONNECT
(MSB) DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
(LSB) DB0
NC
NC
NC
NC
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DB1
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
2–9
10
11–14
15
DB9
DB8–DB1
DB0
NC
SLEEP
Most Significant Data Bit (MSB)
Data Bits 8–1
Least Significant Data Bit (LSB)
No Internal Connection
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
Reference Ground when internal 1.2 V reference used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD).
Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to AGND). Requires
0.1
μ
F capacitor to AGND when internal reference activated.
Full-Scale Current Output Adjust
No Internal Connection
Analog Common
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Reserved. Do Not Connect to Common or Supply.
Analog Supply Voltage (3.3 V)
Selects Input Data Format. Connect to DGND for straight binary, DVDD for two’s complement.
Digital Common
Digital Supply Voltage (3.3 V)
Clock Input. Data latched on positive edge of clock.
16
17
REFLO
REFIO
18
19
20
21
22
23
24
25
26
27
28
FS ADJ
NC
ACOM
IOUTB
IOUTA
RESERVED
AVDD
MODE
DCOM
DVDD
CLOCK
相關(guān)PDF資料
PDF描述
AD9742 12-Bit, 165 MSPS TxDAC D/A Converter
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