參數(shù)資料
型號(hào): AD9740ARU
廠商: Analog Devices Inc
文件頁(yè)數(shù): 10/32頁(yè)
文件大?。?/td> 0K
描述: IC DAC 10BIT 210MSPS 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
系列: TxDAC®
設(shè)置時(shí)間: 11ns
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 145mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 210M
配用: AD9740ACP-PCBZ-ND - BOARD EVAL FOR AD9740ACP
AD9740
Rev. B | Page 18 of 32
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (that is, VOUTA and VOUTB)
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9740. A
differential resistor, R
B
DIFF
, can be inserted in applications where
the output of the transformer is connected to the load, RLOAD,
via a passive reconstruction filter or cable. RDIFF is determined
by the transformer’s impedance ratio and provides the proper
source termination that results in a low VSWR. Note that
approximately half the signal power is dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-
ended conversion, as shown in Figure 33. The AD9740 is
configured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
AD9740
IOUTA
IOUTB
COPT
500
Ω
225
Ω
225
Ω
500
Ω
25
Ω
25
Ω
AD8047
22
21
02911-031
Figure 33. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the
differential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
off a dual supply because its output is approximately ±1 V. A
high speed amplifier capable of preserving the differential
performance of the AD9740 while meeting other system level
objectives (that is, cost or power) should be selected. The op
amp’s differential gain, gain setting resistor values, and full-scale
output swing capabilities should all be considered when
optimizing this circuit.
The differential circuit shown in Figure 34 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9740 and the op amp, is also used to level shift the
differential output of the AD9740 to midsupply (that is,
AVDD/2). The AD8041 is a suitable op amp for this application.
AD9740
IOUTA
IOUTB
COPT
500
Ω
225
Ω
225
Ω
1k
Ω
25
Ω
25
Ω
AD8041
1k
Ω
AVDD
22
21
02911-032
Figure 34. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 35 shows the AD9740 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly
terminated 50 Ω cable because the nominal full-scale current,
IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 Ω.
In this case, RLOAD represents the equivalent load resistance seen
by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching RLOAD.
Different values of IOUTFS and RLOAD can be selected as long as
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL),
discussed in the Analog Outputs section. For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
AD9740
IOUTA
IOUTB
50
Ω
25
Ω
VOUTA = 0V TO 0.5V
IOUTFS = 20mA
50
Ω
22
21
02911-
033
Figure 35. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 36 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9740 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the Analog
Outputs section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates can be
limited by U1’s slew rate capabilities. U1 provides a negative
unipolar output voltage, and its full-scale output voltage is
simply the product of RFB and IOUTFS. The full-scale output
should be set within U1’s voltage output swing capabilities by
scaling IOUTFS and/or RFB. An improvement in ac distortion
performance can result with a reduced IOUTFS because U1 is
required to sink less signal current.
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