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參數(shù)資料
| 型號： | AD9740 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 165 MSPS TxDAC D/A Converter |
| 中文描述： | 10位，165 MSPS的TxDAC系列D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 743K |
| 代理商： | AD9740 |
REV. 0
AD9740
–11–
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9740.
The positive output compliance range is slightly dependent on the
full-scale output current, I
OUTFS
. It degrades slightly from its
nominal 1.2 V for an I
OUTFS
= 20 mA to 1.0 V for an I
OUTFS
= 2 mA.
The optimum distortion performance for a single-ended or differ-
ential output is achieved when the maximum full-scale signal at
IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9740’s digital section consists of 10 input bit channels
and a clock input. The 10-bit parallel data inputs follow stan-
dard positive binary coding where DB13 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
DVDD
DIGITAL
INPUT
Figure 6. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
165 MSPS. The clock can be operated at any duty cycle that meets
the specified latch pulsewidth. The setup and hold times can also
be varied within the clock cycle as long as the specified minimum
times are met, although the location of these transition edges
may affect digital feedthrough and distortion performance. Best
performance is typically achieved when the input data transitions
on the falling edge of a 50% duty cycle clock.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relation-
ship between the position of the clock edges and the point in
time at which the input data changes. The AD9740 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9740 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 7 shows the relationship of SFDR
to clock placement with different sample rates. Note that at the
lower sample rates, more tolerance is allowed in clock place-
ment, while at higher rates, more care must be taken.
–3
–2
2
–1
0
1
70
80
TIME (ns) OF DATA CHANGE RELATIVE
TO RISING CLOCK EDGE
S
3
60
50
40
65
75
55
45
f
OUT
= 50MHz
f
OUT
= 20MHz
Figure 7. SFDR vs. Clock Placement @ f
OUT
= 20 MHz and
50 MHz
Sleep Mode Operation
The AD9740 has a power-down function that turns off the output
current and reduces the supply current to less than 4 mA over the
specified supply range of 3.0 V to 3.6 V and temperature range.
This mode can be activated by applying a logic level 1 to the SLEEP
pin. The SLEEP pin logic threshold is equal to 0.5
×
AVDD. This
digital input also contains an active pull-down circuit that ensures
the AD9740 remains enabled if this input is left disconnected.
The AD9740 takes less than 50 ns to power down and approximately
5
μ
s to power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9740 is dependent on
several factors that include:
The power supply voltages (AVDD and DVDD)
The full-scale current output I
OUTFS
The update rate f
CLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, I
AVDD
, and the digital supply current, I
DVDD
.
I
AVDD
is directly proportional to I
OUTFS
as shown in Figure 8
and is insensitive to f
CLOCK
. Conversely, I
DVDD
is dependent on
both the digital input waveform, f
CLOCK
, and digital supply
DVDD. Figure 9 shows I
DVDD
as a function of full-scale sine
wave output ratios (f
OUT
/f
CLOCK
) for various update rates with
DVDD = 3.3 V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9740-EB | 10-Bit, 165 MSPS TxDAC D/A Converter |
| AD9740AR | 10-Bit, 165 MSPS TxDAC D/A Converter |
| AD9740ARU | 10-Bit, 165 MSPS TxDAC D/A Converter |
| AD9742 | 12-Bit, 165 MSPS TxDAC D/A Converter |
| AD9742-EB | 12-Bit, 165 MSPS TxDAC D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9740ACP | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 165 MSPS TXDAC D/A CONVERTER - Bulk |
| AD9740ACP-PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 10Bit, 165MSPS TxDAC D/A Converters 制造商:Analog Devices 功能描述:DEV TOOLS, 10BIT, 165MSPS TXDAC D/A CNVRTRS - Bulk |
| AD9740ACP-PCBZ | 功能描述:BOARD EVAL FOR AD9740ACP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9740ACPRL7 | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 10-bit 32-Pin LFCSP EP T/R |
| AD9740ACPZ | 功能描述:IC DAC 10BIT 210MSPS 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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