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參數(shù)資料
| 型號： | AD9731 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 170 MSPS D/A Converter(170MSPS,10位單片D/A轉(zhuǎn)換器) |
| 中文描述： | 10位，170 MSPS的D / A轉(zhuǎn)換（170MSPS，10位單片的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 157K |
| 代理商： | AD9731 |
–3–
REV. 0
AD9731
Parameter
SFDR PERFORMANCE (Narrowband)
13
2 MHz; 2 MHz Span
25 MHz, 2 MHz Span
10 MHz, 5 MHz Span (Clock = 170 MHz)
INT ERMODULAT ION DIST ORT ION
14
F1 = 800 kHz, F2 = 900 kHz
POWER SUPPLY
15
Digital –V Supply Current
T emp
T est Level
Min
T yp
Max
Units
+25
°
C
+25
°
C
+25
°
C
V
V
V
79
61
73
dB
dB
dB
+25
°
C
V
58
dB
+25
°
C
Full
+25
°
C
Full
+25
°
C
Full
+25
°
C
Full
+25
°
C
I
VI
I
VI
I
VI
V
V
V
27
27
45
45
13
15
439
449
100
37
42
53
66
20
22
mA
mA
mA
mA
mA
mA
mW
mW
μ
A/V
Analog –V Supply Current
Digital +V Supply Current
Power Dissipation
PSRR
NOT ES
1
Measured as an error in ratio of full-scale current to current through R
(640
μ
A nominal); ratio is nominally 32. DAC load is virtual ground.
2
Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification.
3
Internal reference output current defines load conditions applied during Internal Reference Voltage test.
4
Full-scale current variations among devices are higher when driving REFERENCE IN directly.
5
Frequency at which a 3 dB change in output of DAC is observed; R
= 50
; 100 mV modulation at midscale.
6
Based on I
= 32 (CONT ROL AMP IN/R
) when using internal control amplifier. DAC load is virtual ground.
7
Measured as voltage settling at midscale transition to
±
0.1%; R
= 50
.
8
Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
9
Peak glitch impulse is measured as the largest area under a single positive or negative transient.
10
Measured with R
= 50
and DAC operating in latched mode.
11
Data must remain stable for specified time prior to rising edge of CLOCK .
12
Data must remain stable for specified time after rising edge of CLOCK .
13
SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
T he frequency span is dc-to-Nyquist unless otherwise noted.
14
Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. T he distortion products
created will manifest themselves at sum and difference frequencies of the two tones.
15
Supply voltages should remain stable within
±
5% for nominal operation.
Specifications subject to change without notice.
CODE 2
CODE 3
CODE 4
CODE 1
CODE 2
DATA
CODE 1
DATA
CODE 3
DATA
CODE 4
DATA
t
S
t
H
pw
MIN
pw
MAX
CLOCK
DATA
ANALOG OUTPUT
CLOCK
ANALOG OUTPUT
t
PD
t
ST
SPECIFIED
ERROR BAND
H
W
GLITCH AREA =
1/2 HEIGHT
3
WIDTH
DETAIL OF SETTLING TIME
Figure 1. Timing Diagrams
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