- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1988 > AD9726BSVZRL (Analog Devices Inc)IC DAC 16IT LVDS 400MSPS 80-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9726BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/24頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 16IT LVDS 400MSPS 80-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TxDAC+® |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 575mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP-EP（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 2 電流，單極 |
| 采樣率（每秒）： | 400M |
| 配用： | AD9726-EBZ-ND - BOARD EVAL FOR AD9726 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
AD9726
Rev. B | Page 23 of 24
sync logic should be resynchronized by asserting SYNCUPD
at the next convenient time.
In manual mode, users can choose when to update the sync
logic. When operating with burst data, issuing a sync update
between active bursts updates the system without risking the
loss of any data. In fact, because SYNCUPD always forces a
resynchronization regardless of operational mode, even users in
fully automatic mode can reduce the possibility of data loss by
occasionally forcing a sync update during idle activity.
If either the data clock or the DAC clock is interrupted for any
reason, a SYNCUPD should always be executed to ensure that
data bus and DAC clock phase alignment remains optimized.
SYNC External Mode
Going beyond manual mode, sync external mode offers a
greater level of control and can be useful if multiple DAC
channels are employed in an application. Enable sync external
mode by asserting the SYNCEXT bit (Bit 5) in SPI Register
0x16. Manual mode must also be enabled.
The four channels into which each incoming data-word is
multiplexed are called quadrants. In any mode, the current
quadrant value can always be read back via SYNCOUT (Bits
[1:0] of SPI Register 0x15). At sync update, the logic chooses the
optimal quadrant and refreshes the value of SYNCOUT.
It is also possible to enter a value into SYNCIN (Bits [4:3] of SPI
Register 0x16). When external mode is enabled, the logic oper-
ates as expected, except that the quadrant value in SYNCIN is
used following an update. This can be used to align delays
between multiple device outputs.
Operating With SPI Disabled
If the SPI_DIS pin is connected high to ADVDD and the SPI is
disabled, the sync logic is placed into manual mode.
SYNCALRM status can then be monitored in hardware via the
unused SPI pin SDO (54), and SYNCUPD requests can be
entered in hardware via the unused SPI pin SCLK (56). If these
two pins are connected together, fully automatic sync operation
can be achieved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9736BBC | IC DAC 14BIT 1.2GSPS 160CSPBGA |
| AD9737ABBCZ | IC DAC 11BIT 2.5GSPS RF 160BGA |
| AD9740ARU | IC DAC 10BIT 210MSPS 28-TSSOP |
| AD9742ACPZ | IC DAC 12BIT 210MSPS 32LFCSP |
| AD9744ACPZ | IC DAC 14BIT 210MSPS 32-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9726-EB | 制造商:Analog Devices 功能描述:EVAL FOR AD9726 - Bulk |
| AD9726-EBZ | 功能描述:BOARD EVAL FOR AD9726 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD972A | 制造商:Analog Devices 功能描述:- Bulk |
| AD9731 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:10-Bit, 170 MSPS D/A Converter |
| AD9731/PCB | 制造商:Analog Devices 功能描述:EVAL BOARDS FOR 10 BIT 125MHZ DAC - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。