- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373965 > AD9725BSV (ANALOG DEVICES INC) 14-Bit, 600+ MSPS D/A Converter PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9725BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 600+ MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PQFP80 |
| 封裝： | MS-026-ADD-HD, TQFP-80 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 267K |
| 代理商： | AD9725BSV |
Preliminary Technical Data
AD9725
SERIAL PORT INTERFACE REGISTER MAPS
Table 5. Mode Control via SPI Port
Address
Bit 7
Bit 6
COMMS
00
SDIODIR
DATADIR
01
DATA
02
DATAFMT
DDR
03
04
05
06
07
08
09
0A
0B
0C
VERSION
0D
RESERVED
RESERVED
CALMEMCK
0E
RESERVED
RESERVED
MEMRDWR
0F
CALSTAT
CALEN
MEMADDR
10
MEMADDR[7]
MEMADDR[6]
MEMDATA
11
RESERVED
RESERVED
Rev. PrA | Page 9 of 16
Bit 5
SWRST
DCLKPOLI
RESERVED
CALMEM[1]
XFERSTAT
MEMADDR[5]
MEMDATA[5]
Bit 4
SLEEP
RESERVED
DCLKPOLO
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CALMEM[0]
XFEREN
MEMADDR[4]
MEMDATA[4]
Bit 3
PDN
DISDCLKO
VERSION[3]
RESERVED
SMEMWR
MEMADDR[3]
MEMDATA[3]
Bit 2
RESERVED
1
SYNCMAN
VERSION[2]
CALCKDIV[2]
SMEMRD
MEMADDR[2]
MEMDATA[2]
Bit 1
RESERVED
SYNCUPD
VERSION[1]
CALCKDIV[1]
FMEMRD
MEMADDR[1]
MEMDATA[1]
Bit 0
EXREF
SYNCALRM
VERSION[0]
CALCKDIV[0]
UNCAL
MEMADDR[0]
MEMDATA[0]
1
Reserved registers should be set to Logic 0 (low state) during a write operation, and masked (ignored) during a read operation.
Table 6. SPI Register Definitions
Register
COMMCTRL(00)
SDIODIR
Bit
7
Direction
1
Default
0
Description
0: SDIO pin configured for input only during data
transfer
1: SDIO pin configured for input or output during data
transfer
0: Serial data uses MSB first format
1: Serial data uses LSB first format
1: Default all serial register bits, except address 00h
1: DAC output current off
1: All analog and digital circuitry, except serial
interface, off
RESERVED
RESERVED
0: Internal bandgap reference
0: Twos complement input data format
1: Unsigned binary input data format
0: Single Data Rate mode
1: Double Data Rate mode
0: Data latched on DATACLKIN rising edge
1: Data latched on DATACLKIN falling edge
0: Data latched on DATACLKOUT rising edge
1: Data latched on DATACLKOUT falling edge
0: DATACLKOUT enabled
1: DATACLKOUT disabled
0: Automatic synchronization initiated following a
SYNCALRM
1: Manual synchronization needed following a
SYNCALRM
DATADIR
6
1
0
SWRST
SLEEP
PDN
5
4
3
1
1
1
0
0
0
RESERVED
RESERVED
EXREF
DATACTRL(02)
DATAFMT
2
1
0
7
0
0
1
1
0
0
0
0
DDR
6
1
0
DCLKPOLI
5
1
0
DCLKPOLO
4
1
0
DISDCLKO
3
1
0
SYNCMAN
2
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9731BR | 10-Bit, 170 MSPS D/A Converter |
| AD9731BRS | 10-Bit, 170 MSPS D/A Converter |
| AD9731-PCB | 10-Bit, 170 MSPS D/A Converter |
| AD9731 | 10-Bit, 170 MSPS D/A Converter(170MSPS,10位單片D/A轉(zhuǎn)換器) |
| AD9732 | 10-Bit, 200 MSPS D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9726 | 制造商:Analog Devices 功能描述:16-BIT, 600 MSPS TXDAC+? D/A CONVERTER - Bulk |
| AD9726BST | 制造商:Analog Devices 功能描述:16-BIT, 600+ MSPS D/A CONVERTER - Bulk |
| AD9726BSV | 制造商:Analog Devices 功能描述:DAC 1CH 16BIT 80TQFP EP - Bulk |
| AD9726BSVRL | 制造商:Analog Devices 功能描述:DAC 1CH 16BIT 80TQFP EP - Tape and Reel |
| AD9726BSVZ | 功能描述:IC DAC 16IT LVDS 400MSPS 80-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。