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參數(shù)資料
| 型號(hào)： | AD9715-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | ADC 12BIT DUAL 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9715 |
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AD9714/AD9715/AD9716/AD9717
Rev. A | Page 47 of 80
USING THE INTERNAL TERMINATION RESISTORS
The AD9717/AD9716/AD9715/AD9714 have four 500 Ω
termination internal resistors (two for each DAC output).
To use these resistors to convert the DAC output current to a
voltage, connect each DAC output pin to the adjacent load pin.
For example, on the I DAC, IOUTP must be shorted to RLIP
and IOUTN must be shorted to RLIN. In addition, the CMLI
or CMLQ pin must be connected to ground directly or through
a resistor. If the output current is at the nominal 2 mA and the
CMLI or CMLQ pin is tied directly to ground, this produces a
dc common-mode bias voltage on the DAC output equal to 0.5 V.
If the DAC dc bias must be higher than 0.5 V, an external
resistor can be connected between the CMLI or CMLQ pin and
ground. This part also has an internal common-mode resistor
that can be enabled. This is explained in the Using the Internal
Common-Mode Resistor section.
07
26
5-
05
7
I DAC
OR
Q DAC
RCML
CML
RLIN
IOUTN
IOUTP
RLIP
500
Figure 101. Simplified Internal Load Options
Using the Internal Common-Mode Resistor
These devices contain an adjustable internal common-mode
resistor that can be used to increase the dc bias of the DAC
outputs. By default, the common-mode resistor is not con-
nected. When enabled, it can be adjusted from ~250 Ω to
~1 kΩ. Each main DAC has an independent adjustment
using the lower six bits in Register 0x05 (IRCML[5:0]) and
Register 0x08 (QRCML[5:0]).
1200
1100
1000
900
800
700
600
500
400
300
200
0
8
16
24
32
40
48
56
CODE
RE
S
IS
T
A
NCE
(
)
07
26
5-
0
58
Figure 102. Typical CML Resistor Value vs. Register Code
Using the CMLx Pins for Optimal Performance
The CMLx pins also serve to change the DAC bias voltages
in the parts allowing them to run at higher dc output bias
voltages. When running the bias voltage below 0.9 V and an
AVDD of 3.3 V, the parts perform optimally when the CMLx
pins are tied to ground. When the dc bias increases above 0.9 V,
set the CMLx pins at 0.5 V for optimal performance. The maxi-
mum dc bias on the DAC output should be kept at or below 1.2 V
when the supply is 3.3 V. When the supply is 1.8 V, keep the dc
bias close to 0 V and connect the CMLx pins directly to ground.
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| AD9716BCPZRL7 | 功能描述:IC DAC DUAL 12BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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