參數(shù)資料
型號: AD9709
廠商: Analog Devices, Inc.
英文描述: 8-Bit, 125 MSPS Dual TxDAC D/A Converter
中文描述: 8位,125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換
文件頁數(shù): 13/27頁
文件大?。?/td> 466K
代理商: AD9709
REV. 0
AD9709
–13–
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE
ns
S
0
4
2
0
2
3
3
1
4
1
10
20
30
40
50
60
Figure 29. SINAD vs. Clock Placement @ f
OUT
= 20 MHz
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9709 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock/data placement.
SLEEP MODE OPERATION
The AD9709 has a power down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 3.0 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level 1 to the SLEEP pin. The SLEEP pin logic threshold
is equal to 0.5
×
AVDD. This digital input also contains an
active pull-down circuit that ensures the AD9709 remains
enabled if this input is left disconnected. The AD9709 takes
less than 50 ns to power down and approximately 5
μ
s to
power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9709 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output I
OUTFS
,
(3) the update rate f
CLOCK
, (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, I
AVDD
, and the digital supply cur-
rent, I
DVDD
. I
AVDD
is directly proportional to I
OUTFS
as shown in
Figure 30 and is insensitive to f
CLOCK
.
Conversely, I
DVDD
is dependent on both the digital input wave-
form, f
CLOCK
, and digital supply DVDD. Figures 31 and 32
show I
DVDD
as a function of full-scale sine wave output ratios
(f
OUT
/f
CLOCK
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how I
DVDD
is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
APPLYING THE AD9709
Output Configurations
The following sections illustrate some typical output configura-
tions for the AD9709. Unless otherwise noted, it is assumed
that I
OUTFS
is set to a nominal 20 mA. For applications requiring
the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti-
mum high-frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling,
a bipolar output, signal gain and/or level shifting, within the
bandwidth of the chosen op amp.
I
OUTFS
mA
0
5
10
10
I
A
20
30
40
50
60
70
80
15
20
25
Figure 30. I
AVDD
vs. I
OUTFS
RATIO
f
OUT
/f
CLK
0
0.1
0
I
D
5
10
15
20
25
30
35
0.2
0.3
0.4
0.5
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
Figure 31. I
DVDD
vs. Ratio @ DVDD = 5 V
RATIO
f
OUT
/f
CLK
0
0.1
0
I
D
2
4
6
8
10
12
14
0.2
0.3
0.4
0.5
16
18
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
Figure 32. I
DVDD
vs. Ratio @ DVDD = 3 V
相關(guān)PDF資料
PDF描述
AD9709AST RES 0.01 OHM MAX 25 AMP AXIAL
AD9709-EB 8-Bit, 125 MSPS Dual TxDAC D/A Converter
AD9712B RES,0.0,0.25W,METAL FILM,0%
AD9712BAN RES,0.0,0.25W,METAL FILM,0%
AD9712BAP TEST POINT, WHITE, 0.040 HOLE, 0.062 PCB
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