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參數(shù)資料
| 型號(hào)： | AD96687TQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Ultrafast Comparators |
| 中文描述： | DUAL COMPARATOR, 3000 uV OFFSET-MAX, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | AD96687TQ |
AD96685/AD96687
–3–
REV. C
FUNCT IONAL DE SCRIPT ION
Pin Name
Description
+V
S
NONINVERT ING INPUT
Positive supply terminal, nominally +5.0 V.
Noninverting analog input of the differential input stage. T he NONINVERT ING INPUT must be
driven in conjunction with the INVERT ING INPUT .
Inverting analog input of the differential input stage. T he INVERT ING INPUT must be driven in
conjunction with the NONINVERT ING INPUT .
In the “compare” mode (logic HIGH), the output will track changes at the input of the compara-
tor. In the “l(fā)atch” mode (logic LOW), the output will reflect the input state just prior to the
comparator being placed in the “l(fā)atch” mode.
LATCH ENABLE
must be driven in conjunction
with LAT CH ENABLE for the AD96687.
In the “compare” mode (logic LOW), the output will track changes at the input of the comparator.
In the “l(fā)atch” mode (logic HIGH), the output will reflect the input state just prior to the compara-
tor being placed in the “l(fā)atch” mode. LAT CH ENABLE must be driven in conjunction with
LATCH ENABLE
for the AD96687.
Negative supply terminal, nominally –5.2 V.
One of two complementary outputs. Q will be at logic HIGH if the analog voltage at the
NONINVERT ING INPUT is greater than the analog voltage at the INVERT ING INPUT (pro-
vided the comparator is in the “compare” mode). See LAT CH ENABLE and LAT CH ENABLE
(AD96687 only) for additional information.
One of two complementary outputs.
Q
will be at logic LOW if the analog voltage at the
NONINVERT ING INPUT is greater than the analog voltage at the INVERT ING INPUT
(provided the comparator is in the “compare” mode). See LAT CH ENABLE and LAT CH EN-
ABLE (AD96687 only) for additional information.
One of two grounds, but primarily associated with the digital ground. Both grounds should be con-
nected together near the comparator.
One of two grounds, but primarily associated with the analog ground. Both grounds should be con-
nected together near the comparator.
INVERT ING INPUT
LAT CH ENABLE
LATCH ENABLE
–V
S
Q
Q
GROUND 1
GROUND 2
PIN DE SIGNAT IONS
AD96685BQ/T Q/BR
AD96687BQ/T Q/BR
AD96685BP
AD96685BH
AD96687BP
NC = NO CONNECT
NC = NO CONNECT
NC = NO CONNECT
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