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參數(shù)資料
| 型號(hào)： | AD96687BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP DUAL 2.5NS 16-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 05/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 2 |
| 輸出類型： | 補(bǔ)充型，ECL，開路發(fā)射極 |
| 電壓 - 輸入偏移（最小值）： | 2mV @ -5.2V，5V |
| 電流 - 輸入偏壓（最小值）： | 10µA @ -5.2V，5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 18mA，36mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 90dB CMRR，70dB PSRR |
| 傳輸延遲（最大）： | 3.5ns |
| 工作溫度： | -25°C ~ 85°C |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
REV. D
–3–
AD96685/AD96687
ABSOLUTE MAXIMUM RATINGS
1
Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . –6.5 V
Input Voltage Range
2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Latch Enable Voltage . . . . . . . . . . . . . . . . . . . . . . . . –VS to 0 V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
3
AD96685BR/AD96687BQ/BR/BP . . . . . . . –25
°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –55
°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175
°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . . 300
°C
NOTES
1Absolute maximum ratings are limiting values, may be applied individually, and
beyond which serviceability of the circuit may be impaired. Functional operation
under any of these conditions is not necessarily implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Under no circumstances should the input voltages exceed the supply voltages.
3Typical thermal impedances . . .
AD96685 SOIC
qJA = 170
°C/W; q
JC = 60
°C/W
AD96687 Ceramic
qJA = 115
°C/W; q
JC = 57
°C/W
AD96687 SOIC
qJA = 92
°C/W; q
JC = 47
°C/W
AD96687 PLCC
qJA = 81
°C/W; q
JC = 45
°C/W
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% production tested.
II – 100% production tested at 25
°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25
°C; 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
FUNCTIONAL DESCRIPTION
Pin Name
Description
+VS
Positive supply terminal, nominally 5.0 V.
NONINVERTING INPUT
Noninverting analog input of the differential input stage. The NONINVERTING INPUT must be
driven in conjunction with the INVERTING INPUT.
INVERTING INPUT
Inverting analog input of the differential input stage. The INVERTING INPUT must be driven in
conjunction with the NONINVERTING INPUT.
LATCH ENABLE
In the “compare” mode (logic HIGH), the output will track changes at the input of the compara-
tor. In the “l(fā)atch” mode (logic LOW), the output will reflect the input state just prior to the
comparator being placed in the “l(fā)atch” mode. LATCH ENABLE must be driven in conjunction
with LATCH ENABLE for the AD96687.
LATCH ENABLE
In the “compare” mode (logic LOW), the output will track changes at the input of the comparator.
In the “l(fā)atch” mode (logic HIGH), the output will reflect the input state just prior to the comparator
being placed in the “l(fā)atch” mode. LATCH ENABLE must be driven in conjunction with
LATCH ENABLE for the AD96687.
–VS
Negative supply terminal, nominally –5.2 V.
Q
One of two complementary outputs. Q will be at logic HIGH if the analog voltage at the
NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT (pro-
vided the comparator is in the “compare” mode). See LATCH ENABLE and LATCH ENABLE
(AD96687 only) for additional information.
Q
One of two complementary outputs. Q will be at logic LOW if the analog voltage at the
NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT
(provided the comparator is in the “compare” mode). See LATCH ENABLE and LATCH ENABLE
(AD96687 only) for additional information.
GROUND 1
One of two grounds, but primarily associated with the digital ground. Both grounds should be
connected together near the comparator.
GROUND 2
One of two grounds, but primarily associated with the analog ground. Both grounds should be
connected together near the comparator.
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| AD96687BRZ | 功能描述:IC COMPARATOR DUAL 2.5NS 16-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標(biāo)準(zhǔn)）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標(biāo)準(zhǔn)）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
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