參數(shù)資料
型號(hào): AD9649BCPZRL7-40
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 23/32頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 40MSPS 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 14
采樣率(每秒): 40M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 65.8mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,單極;1 個(gè)差分,單極
AD9649
Rev. 0 | Page 3 of 3
2
GENERAL DESCRIPTION
The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit,
20/40/65/80 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and an on-chip volt-
age reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
A differential clock input with optional 1, 2, or 4 divide ratios
controls all internal conversion cycles.
The digital output data is presented in offset binary, gray code, or
twos complement format. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic. Both 1.8 V and
3.3 V CMOS levels are supported.
The AD9649 is available in a 32-lead RoHS-compliant LFCSP and
is specified over the industrial temperature range (40°C to
+85°C).
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