參數(shù)資料
型號(hào)： AD9637BCPZ-40
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC OCTAL 12 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 40M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 414mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 8 個(gè)差分
AD9637
Data Sheet
Rev. A | Page 20 of 40
If the internal reference of the AD9637 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 48 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
3.0
2.5
2.0
1.5
1.0
0.5
V
RE
F
E
RRO
R
(
%)
LOAD CURRENT (mA)
INTERNAL VREF = 1V
10215-
047
Figure 48. VREF Error vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 49 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
10215-
048
4
–8
–40
85
V
RE
F
E
RRO
R
(
mV
)
TEMPERATURE (°C)
–6
–4
–2
0
2
–15
10
35
60
Figure 49. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 k load (see Figure 42). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V. It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9637 sample clock inputs,
CLK+ and CLK, with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK pins via a transformer or
capacitors. These pins are biased internally (see Figure 36) and
require no external bias.
Clock Input Options
The AD9637 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the utmost concern, as described in the Jitter Considerations
section.
Figure 50 and Figure 51 show two preferred methods for clocking
the AD9637 (at clock rates of up to 640 MHz prior to the internal
CLK divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 80 MHz and 640 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9637 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9637 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance. However, the diode capacitance comes
into play at frequencies above 500 MHz. Care must be taken in
choosing the appropriate signal limiting diode.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
10215-
049
Figure 50. Transformer Coupled Differential Clock (Up to 200 MHz)
0.1F
CLOCK
INPUT
0.1F
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
10215-
050
Figure 51. Balun Coupled Differential Clock (80 MHz to 640 MHz)
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