參數(shù)資料
型號： AD9637-80EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 17/40頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9637
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9637
Data Sheet
Rev. A | Page 24 of 40
Figure 59 shows an example of the LVDS output using the
ANSI-644 standard (default) data eye and a time interval error
(TIE) jitter histogram with trace lengths of less than 24 inches
on standard FR-4 material.
10215-
058
0.5k
1.0k
1.5k
3.0k
2.5k
2.0k
0
–60p
s
–40p
s
–20p
s
0p
s
20p
s
40p
s
60p
s
80p
s
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
300
200
100
–300
–200
–100
0
–0.
8n
s
0.
8n
s
–0.
6n
s
0.
6n
s
–0.
4n
s
0.
4n
s
–0.
2n
s
0.
2n
s
0n
s
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 8000:448000
Figure 59. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4, External 100 Far-End
Termination Only
Figure 60 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Note that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
It is the responsibility of the user to determine if the waveforms
meet the timing budget of the design when the trace lengths exceed
24 inches. Additional SPI options allow the user to further increase
the internal termination (increasing the current) of all eight outputs
to drive longer trace lengths, which can be achieved by program-
ming Register 0x15. Even though this option produces sharper
rise and fall times on the data edges and is less prone to bit errors,
it also increases the power dissipation of the DRVDD supply.
10215-
059
0.5k
1.0k
1.5k
3.0k
2.5k
2.0k
0
–60p
s
–40p
s
–20p
s
0p
s
20p
s
40p
s
60p
s
80p
s
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
300
200
100
–300
–200
–100
0
–0.
8n
s
0.
8n
s
–0.
6n
s
0.
6n
s
–0.
4n
s
0.
4n
s
–0.
2n
s
0.
2n
s
0n
s
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 7000:448000
Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4, External 100 Far Termination Only
The default format of the output data is twos complement. Table 10
shows an example of the output coding format. To change the
output data format to offset binary, see the Memory Map section.
Data from each ADC is serialized and provided on a separate
channel in DDR mode. The data rate for each serial stream is equal
to 12 bits times the sample clock rate, with a maximum of
960 Mbps (12 bits × 80 MSPS) = 960 Mbps. The lowest typical
conversion rate is 10 MSPS. See the Memory Map section for
details on enabling this feature.
Table 10. Digital Output Coding
Input (V)
Condition (V)
Offset Binary Output Mode
Twos Complement Mode
VIN+ VIN
< VREF 0.5 LSB
0000 0000 0000
1000 0000 0000
VIN+ VIN
= VREF
0000 0000 0000
1000 0000 0000
VIN+ VIN
= 0
1000 0000 0000
0000 0000 0000
VIN+ VIN
= +VREF 1.0 LSB
1111 1111 1111
0111 1111 1111
VIN+ VIN
> +VREF 0.5 LSB
1111 1111 1111
0111 1111 1111
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