參數(shù)資料
型號: AD9633BCPZRL7-80
廠商: Analog Devices Inc
文件頁數(shù): 4/40頁
文件大小: 0K
描述: IC ADC 12BIT SRL 80MSPS 48LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: LVDS,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 389mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-WQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)差分,雙極
AD9633
Data Sheet
Rev. 0 | Page 12 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
VIN+A
VIN–A
AVDD
4
PDWN
5
CSB
6
SDIO/OLM
7
SCLK/DTP
24
D
0+
B
23
D
0–
B
22
D
1+
B
21
D
1–
B
20
F
C
O
+
19
F
C
O
18
D
C
O
+
17
D
C
O
16
D
0+
C
15
D
0–
C
14
D
1+
C
13
D
1–
C
44
S
Y
N
C
45
A
V
D
46
A
V
D
47
V
IN
–C
48
V
IN
+
C
43
V
C
M
42
V
R
E
F
41
S
E
N
S
E
40
R
B
IA
S
39
A
V
D
38
V
IN
–B
37
V
IN
+
B
25
D0+D
26
D0–D
27
D1+D
28
D1–D
29
DRVDD
30
AVDD
31
CLK+
32
CLK–
33
AVDD
34
AVDD
35
VIN–D
36
VIN+D
8
DRVDD
9
D0+A
10
D0–A
11
D1+A
12
D1–A
AD9633
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE
PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OPERATION.
1
0073
-007
Figure 9. 48-Lead LFCSP Pin Configuration, Top View
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0
AGND,
Exposed Pad
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides
the analog ground for the part. This exposed pad must be connected to ground for proper
operation.
1
VIN+D
ADC D Analog Input True.
2
VIND
ADC D Analog Input Complement.
3, 4, 7, 34, 39, 45, 46
AVDD
1.8 V Analog Supply Pins.
5, 6
CLK, CLK+
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
8, 29
DRVDD
Digital Output Driver Supply.
9, 10
D1D, D1+D
Channel D Digital Outputs.
11, 12
D0D, D0+D
Channel D Digital Outputs.
13, 14
D1C, D1+C
Channel C Digital Outputs.
15, 16
D0C, D0+C
Channel C Digital Outputs.
17, 18
DCO, DCO+
Data Clock Outputs.
19, 20
FCO, FCO+
Frame Clock Outputs.
21, 22
D1B, D1+B
Channel B Digital Outputs.
23, 24
D0B, D0+B
Channel B Digital Outputs.
25, 26
D1A, D1+A
Channel A Digital Outputs.
27, 28
D0A, D0+A
Channel A Digital Outputs.
30
SCLK/DTP
SPI Clock Input/Digital Test Pattern.
31
SDIO/OLM
SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.
32
CSB
SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.
33
PDWN
Digital Input, 30 kΩ Internal Pull-Down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
35
VINA
ADC A Analog Input Complement.
36
VIN+A
ADC A Analog Input True.
37
VIN+B
ADC B Analog Input True.
38
VINB
ADC B Analog Input Complement.
40
RBIAS
Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
41
SENSE
Reference Mode Selection.
42
VREF
Voltage Reference Input and Output.
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