參數(shù)資料
型號： AD9633BCPZ-105
廠商： Analog Devices Inc
文件頁數(shù)： 18/40頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 105MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 473mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 4 個差分，雙極
Data Sheet
AD9633
Rev. 0 | Page 25 of 40
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
Input Clock Divider
The AD9633 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9633 clock divider can be synchronized using the
external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a vari-
ety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9633 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9633. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 63.
73
55
40
60
S
NRF
S
(
d
B
F
S
)
DUTY CYCLE (%)
10
073
-06
9
63
61
57
59
65
67
71
69
42
44
46
48
50
52
54
56
58
SNRFS (DCS OFF)
SNRFS (DCS ON)
Figure 63. SNR vs. DCS On/Off
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
100
0.1F
240
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
100
73-
066
Figure 64. Differential PECL Sample Clock (Up to 1 GHz)
100
0.1F
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
100
73-
067
Figure 65. Differential LVDS Sample Clock (Up to 1 GHz)
OPTIONAL
100
0.1F
501
150 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
100
73-
0
68
Figure 66. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
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