參數(shù)資料
型號： AD9629-40EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 21/32頁
文件大?。?/td> 0K
描述： BOARD EVALUATION AD9629 40MSPS
設(shè)計資源： AD9649/29/09 Schematics
AD9649/29/09 Gerber Files
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 2 Vpp
在以下條件下的電源（標準）： 60.5mW @ 40MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9629
已供物品： 板
AD9629
Rev. 0 | Page 28 of 32
Addr
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
0x14
Output mode
00 = 3.3 V CMOS
10 = 1.8 V CMOS
Open
Output
disable
Open
Output
invert
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
0x00
Configures the
outputs and the
format of the data
0x15
Output adjust
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V DCO
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
0x22
Determines CMOS
output drive
strength properties
0x16
Output phase
DCO
Output
polarity
0 =
normal
1 =
inverted
Open
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
0x00
On devices that
utilize global clock
divide, determines
which phase of the
divider output is
used to supply the
output clock;
internal latching is
unaffected
0x17
Output delay
Enable
DCO
delay
Open
Enable
data
delay
Open
DCO/data delay, Bits[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
0x00
Sets the fine output
delay of the output
clock, but does not
change internal
timing
0x19
USER_PATT1_LSB
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-defined
pattern, 1 LSB
0x1A
USER_PATT1_MSB
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
pattern, 1 MSB
0x1B
USER_PATT2_LSB
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-defined
pattern, 2 LSB
0x1C
USER_PATT2_MSB
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
pattern, 2 MSB
0x24
BIST signature LSB
BIST signature, Bits[7:0]
0x00
Least significant byte
of BIST signature,
read only
0x2A
OR/MODE select
Open
0 =
MODE
1 = OR
(default)
0x01
Selects I/O
functionality in
conjunction w/
Address 0x08 for
MODE (input) or OR
(output) on external
Pin 23
1.1. AD9629 Specific Customer SPI Control
0x101
USR2
1
Open
Enable
GCLK
detect
Run GCLK
Open
Disable
SDIO
pull-
down
0x88
Enables internal
oscillator for clock
rates of <5 MHz
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AD9629-65EBZ 功能描述:BOARD EVALUATION AD9629 65MSPS RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
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AD9629-80EBZ 功能描述:BOARD EVALUATION AD9629 80MSPS RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
AD9629-80EBZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
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