參數(shù)資料
型號: AD9629-20EBZ
廠商: Analog Devices Inc
文件頁數(shù): 22/32頁
文件大小: 0K
描述: BOARD EVALUATION AD9629 20MSPS
設計資源: AD9649/29/09 Schematics
AD9649/29/09 Gerber Files
標準包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 20M
數(shù)據接口: 串行,SPI?
輸入范圍: 2 Vpp
在以下條件下的電源(標準): 47.5mW @ 20MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9629
已供物品:
AD9629
Rev. 0 | Page 29 of 32
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
USR2 (Register 0x101)
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below about 5 MSPS. When a low encode rate is detected,
an internal oscillator, GCLK, is enabled ensuring the proper
operation of several circuits. If set low the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
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