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參數(shù)資料
| 型號(hào)： | AD9627ABCPZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 47/76頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 1255MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；2 個(gè)差分，單極 |
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AD9627
Rev. B | Page 51 of 76
EVALUATION BOARD
The AD9627 evaluation board provides all of the support circuitry
required to operate the ADC in its various modes and configura-
tions. The converter can be driven differentially through a double
balun configuration (default) or optionally through the AD8352
differential driver. The ADC can also be driven in a single-ended
fashion. Separate power pins are provided to isolate the DUT
from the AD8352 drive circuitry. Each input configuration can
be selected by proper connection of various components (see
characterization setup used to evaluate the ac performance of
the AD9627.
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
See Figure 75 to Figure 79 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The output of the supply is a 2.1 mm inner diameter
circular jack that connects to the PCB at J16. Once on the PC
board, the 6 V supply is fused and conditioned before connection
to six low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
External supplies can be used to operate the evaluation board
by removing L1, L3, L4, and L13 to disconnect the voltage
regulators supplied from the switching power supply. This enables
the user to individually bias each section of the board. Use P3
and P4 to connect a different supply for each section. At least
one 1.8 V supply is needed with a 1 A current capability for
AVDD and DVDD; a separate 1.8 V to 3.3 V supply is recom-
mended for DRVDD. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP VDD) with
a 1 A current capability is needed. To operate the evaluation board
using the alternate SPI options, a separate 3.3 V analog supply
(VS) is needed, in addition to the other supplies. The 3.3 V
supply (VS) should have a 1 A current capability, as well. Solder
Jumper SJ35 allows the user to separate AVDD and DVDD,
if desired.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz
SMA100A signal generators or the equivalent. Use 1 m long,
shielded, RG-58, 50 Ω coaxial cable for making connections to the
evaluation board. Enter the desired frequency and amplitude for
the ADC. The AD9627 evaluation board from Analog Devices,
Inc., can accept a ~2.8 V p-p or 13 dBm sine wave input for the
clock. When connecting the analog input source, it is recom-
mended that a multipole, narrow-band, band-pass filter with 50 Ω
terminations be used. Band-pass filters of this type are available
from TTE, Allen Avionics, and K&L Microwave, Inc. Connect the
filter directly to the evaluation board, if possible.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog
Devices standard ADC data capture board (HSC-ADC-EVALCZ).
For more information on the ADC data capture boards and their
optional settings, visit www.analog.com/FIFO.
USB
CONNECTION
AD9627
EVALUATION BOARD
12-BIT
PARALLEL
CMOS
12-BIT
PARALLEL
CMOS
HSC-ADC-EVALCZ
FPGA BASED
DATA
CAPTURE BOARD
PC RUNNING
VISUAL ANALOG
AND SPI
CONTROLLER
SOFTWARE
1.8V
–+
AV
DD
I
N
VS
DRV
D
I
N
GN
D
GN
D
–+
5.0V
GN
D
AM
P
V
DD
3.3V
6V DC
2A MAX
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
–+
GN
D
3.3V
VC
P
–+
GN
D
3.3V
SPI
06
57
1-
07
4
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
CLK
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
AINB
BAND-PASS
FILTER
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
AINA
BAND-PASS
FILTER
Figure 74. Evaluation Board Connection
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| AD9627ABCPZ-150 | 功能描述:IC ADC 12BIT 150MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9627ABCPZ-80 | 功能描述:IC ADC 12BIT 80MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9627BCPZ-105 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 105Msps 12-bit Parallel/LVDS 64-Pin LFCSP EP |
| AD9627BCPZ11-105 | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AD9627BCPZ11-150 | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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