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參數(shù)資料
| 型號： | AD9577BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN PLL DUAL 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PCI Express® (PCIe) |
| 類型： | 扇出緩沖器（分配），網(wǎng)絡(luò)時鐘發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，PCI Express（PCIe），SONET/SDH |
| 輸入： | 時鐘，晶體 |
| 輸出： | LVCMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 637.5MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-WQ（6x6） |
| 包裝： | 托盤 |
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Data Sheet
AD9577
Rev. 0 | Page 41 of 44
The AD9577 acts as a standard slave device on the bus. The data
on the SDA pin is eight bits long supporting the 7-bit addresses
plus the R/W bit. The
has 31 subaddresses to enable
the user-accessible internal registers (see
). Therefore, it
interprets the first byte as the device address and the second byte as
the starting subaddress. Auto-increment mode is supported, which
allows data to be read from or written to the starting subaddress
and each subsequent address without manually addressing the
subsequent subaddress. A data transfer is always terminated by
a stop condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the data
transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCL high period, one start
condition, one stop condition, or a single stop condition followed
by a single start condition should be issued. If an invalid subaddress
is issued, the AD9577 does not issue an acknowledge and returns
to the idle condition. If the highest subaddress is exceeded while
reading back in auto-increment mode, the highest subaddress
register contents continue to be output until the master device
issues a no acknowledge, which indicates the end of a read. In a no
acknowledge condition, the SDA line is not pulled low on the ninth
transfers, and see Figure 47 for a more detailed timing diagram.
To overwrite any of the default register values, complete the
following steps:
1.
Enable the overwriting of registers by setting EnI2C,
Register C0[1].
2.
Only write to registers that need modification from their
default value.
3.
After all the registers have been set, a new acquisition is
initiated by toggling NewAcq, Register X0[0] from low to high
to low.
An example set of I2C commands follows. These enable the I2C
registers and program the output frequencies of both PLLs. fPFD
is 25 MHz. A leading W represents a write command.
Table 32. I2C Programming Example Register Writes
Write/Read
Register Name
Data (Hex)
Operation
W
C0
02
Enable I2C registers
W
AF0
0A
Na = 80 + 10 = 90; fVCO1 = 2.25 GHz
W
ADV0
A6
Channel 0 divides by 5 × 6 = 30; fOUT0 = 75 MHz
W
ADV1
CC
Channel 1 divides by 6 × 12 = 72; fOUT1 = 31.25 MHz
W
BF3
15
Nb = 80 + 21 = 101; FVCO2 = 2.53832 GHz
W
BF0
14
FRAC = 333
W
BF1
D2
FRAC = 333, MOD = 625
W
BF2
71
MOD = 625
W
ABF0
C0
Power-up SDM, release SDM reset
W
BP0
04
Turn on Bleed
W
BDV0
44
Channel 2 divides by 2 × 4 = 8; fOUT2 = 317.29 MHz
W
BDV1
B0
Channel 3 divides by 5 × 16 = 80; fOUT3 = 31.729 MHz
W
X0
01
Force new acquisition by toggling NewAcq
W
X0
00
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| AD9577BCPZ-RL | 功能描述:IC CLK GEN PLL DUAL 40LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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