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參數(shù)資料
| 型號(hào)： | AD9561JR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Pulse Width Modulator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 273K |
| 代理商： | AD9561JR-REEL |
AD9561
–6–
REV. 0
This yields the maximum time from the trailing edge of CAL IN
to the rising edge of CAL OUT. As an example, the maximum
time required for auto-calibration for a system with clock frequency
of 20 MHz is 102.4 ms plus the width of the CAL IN pulse.
Power Reduce
The POWER REDUCE function permits the user to power
down all nonessential circuits when the printer is not active.
Applying a Logic “0” to POWER REDUCE decreases the
power supply requirement by approximately half.
APPLICATIONS
DATA Timing
Input DATA to the AD9561 is double latched. As a result of the
internal timing, the OUTPUT is delayed more than one clock
period from its corresponding DATA word. Figure 6 illustrates
timing of DATA and CONTROL inputs relative to the CLOCK.
SETUP
HOLD
CLOCK
DATA
CONTROL
Figure 6. DATA and CONTROL Timing
The DATA and CONTROL inputs to the AD9561 are stan-
dard master-slave latches. Inputs are latched in on the rising
edge of the CLOCK with 2 ns Set-Up time and 2 ns Hold time.
This is a design improvement over the AD9560 meant to
simplify interfacing the AD9561 to digital processing circuits.
A propagation delay exists between the CLOCK and OUTPUT
pulses. The minimum propagation delay can be observed when
alternating between codes 0 (00
H
hexadecimal) and 255 (FF
H
hexadecimal). This delay is due in part to normal circuit
propagation; the remainder is due to time required to imple-
ment the proprietary ramp function. OUTPUT pulse transi-
tions will typically occur 22 ns after the rising edge of CLOCK.
It may vary from 10 ns–35 ns over temperature.
Transfer Function
Output pulse width increases with increasing DATA values. As
the heavy line of Figure 7 shows, the transfer function of the
AD9561 is slightly nonideal.
CODE
100
80
0
0
25
P
12.5
128
60
40
20
Figure 7. Pulse Width Transfer Function
An ideal transfer would give 0% (or 0 ns) pulse width for a Code 0.
As the code is incremented in steps of one, the pulse width would
increase by 0.39% until it reached 100% for Code 255.
When operating at high clock rates, several of the most narrow
pulses do not reach valid logic Level “1” because of finite rise
time. For example, at 20 MHz, a 1.95% pulse (code 5 or 05
H
)
would have an expected pulse width of 1 ns. Because the rise
time is typically 1.5 ns, this pulse will not reach a full output
level. Therefore, depending on the clock rate, the lowest set of
codes produces a series of triangle waves increasing in width
and amplitude until a pulse of approximately 3 ns–5 ns reaches
a proper logic level. Thus, the transfer is flat until about
3 ns–5 ns pulse width (number of codes varies as a function of
CLOCK frequency).
Because of the new ramp topology in the AD9561, the transfer
function extends slightly greater than 100% (typically 102%) of
the clock period. This has the effect of creating smooth transitions
at the CLOCK period boundaries instead of the discontinuities
produced by the AD9560.
t
PD
TEM
(LEFT JUSTIFIED)
DEM
(CENTER JUSTIFIED)
LEM
(RIGHT JUSTIFIED)
t
CLOCK
t
CLOCK
t
CLOCK
t
CLOCK
Figure 8. Dot Clock Period Transitions
As shown in Figure 8, a Leading Edge Modulated pulse followed
by a Trailing Edge Modulated pulse will stay high from the rising
edge of the first pulse to the falling edge of the second. This is
due to Code 255 being designed to be typically 102% of the
CLOCK period. (Dashed lines indicate where transitions
would occur if the code for the following or preceding period
were 0.) Likewise, no gap occurs for maximum width Trailing
Edge Modulation to max pulse width for Dual Edge Modula-
tion. Because the ending and starting characteristics of all
modes are symmetrical, any combination of pulses that ends at
the boundary of the first period and starts at the boundary of
the second period will produce a continuous pulse across the
boundary.
For the purposes of printing text, or any time absolute white or
black is required, 0 is decoded and a 100% LOW
is output in
the next CLOCK cycle. Similarly, 255 is detected and the next
pulse is 100% HIGH.
Retrace
The RETRACE function permits driving the output to a
constant Logic High. For laser printer applications, applying a
logic “1” to RETRACE holds the laser on during the retrace
period so end of scan can be detected. Returning it to Logic
Low gives control back to the input data bits D0–D7.
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