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參數(shù)資料
| 型號： | AD9561 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Pulse Width Modulator(高速,數(shù)字可調(diào)的PWM) |
| 中文描述： | 脈寬調(diào)制器（高速，數(shù)字可調(diào)的脈寬調(diào)制） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 266K |
| 代理商： | AD9561 |
AD9561
–5–
REV. 0
Pulse Pattern Example
Figure 1 at the top of the previous page illustrates the PWM
OUT of the AD9561 with various DATA and CONTROL
inputs. The DATA format is Binary. In the Pulse Pattern
Example, the Hexadecimal format is used, i.e., FF
H
represents
decimal 255.
The top line shows the CLOCK; the second shows DATA and
CONTROL inputs, which are latched on the rising edge of
CLOCK. The third line shows the resulting pulse.
The AD9561 DATA and CONTROL inputs are double
latched. The OUTPUT pulse labeled “Pulse N” results from
DATA and CONTROL values latched in by the first CLOCK,
illustrating the one CLOCK period timing delay.
The CONTROL value number for pulse one is shown as xx.
This means the value is not important because a 100% pulse
will be output for any CONTROL value for DATA value 255 or
FF
H
. Likewise, OUTPUT Pulse N is noted as 100% DNC (do
not care), also noting that CONTROL value is unimportant.
The fourth DATA/CONTROL value is C0/0X. This indicates
that the level for LEM/TEM is unimportant when SEM/DEM is
logic Level “0”.
Selecting R
SET
Because the AD9561 must provide full range coverage of the
CLOCK pulse period, the ramp time must be matched to the
CLOCK period. All components for the ramp generators, except
R
SET
,
are integrated in the AD9561.
R
SET
, is selected by the user to set the ramp time close to the
CLOCK period. The ramps are generated by constant current
sources charging on-chip capacitors.
R
SET
can be chosen in the range from 226
for 60 MHz
operation to 16.5 k
for 1 MHz. Because the absolute value of
the on-chip capacitor can vary by
±
20%, the autocalibration
circuit is included to fine tune the matching of the ramp time to
the CLOCK period.
R
SET
– k
100
10
10
20
1
C
10
Figure 3. R
SET
Values vs. CLOCK Frequency
Figure 3 shows approximate values for R
SET
over the operating
frequency range. The following equation should be used to
determine R
SET
:
R
=
30.2068
×
10
9
F
1.04414
where
F
is the CLOCK frequency in Hz. The resistor value
determined by the equation will generate a current near center-
range of the autocalibration circuit.
Autocalibration
The AD9561 should be calibrated when power is applied to the
system or after a power reduce cycle.
t
AC
CAL START
CAL OUT
1μs MIN
Figure 4. Autocalibration Timing
Autocalibration is initiated by applying a pulse of 1
μ
s minimum
duration to Pin 17, CAL START.
The CLOCK pulse should be
applied continuously during calibration
.
As Figure 4 shows, the
initial state of CAL OUT is not known.
During the CAL IN pulse, all internal logic is initialized for
calibration and proper synchronization once calibration is
complete; the falling edge of CAL IN initiates the Auto-CAL
cycle.
Auto-CAL is not affected by the code applied to the DATA or
CONTROL inputs. However, to assure that no pulses are
generated during calibration, it is suggested that all digital
inputs be held at Logic “0.”
On the falling edge of CAL IN, the ramp’s slope is set as slow as
possible for the current R
SET
. Figure 4 shows the RAMP slope
increasing as autocalibration adds small incremental currents,
until it crosses the internal REF LO before the end of the
CLOCK period.
RAMP
REF LO
RAMP
END OF CLOCK CYCLE
TIME
Figure 5. Autocalibration Conceptual
The calibration current is incremented on each 32nd CLOCK
pulse until the full-scale ramp time is equal to the period of the
CLOCK. Cal Complete is detected and CAL OUT goes high
when the ramp crosses REF LO before it is reset by the next
CLOCK. With a maximum of 64 incremental increases, the
maximum autocalibration time, t
AC
, can be calculated by the
equation:
t
AC
=
32
×
64
where:
F
C
= CLOCK frequency in Hertz
F
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