參數(shù)資料
型號： AD9558BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 86/104頁
文件大?。?/td> 0K
描述： IC CLK XLATR PLL 1250MHZ 64LFCSP
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
標準包裝： 750
類型： 時鐘/頻率轉換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 4:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9558
Data Sheet
Rev. B | Page 82 of 104
Table 68. Distribution OUT0 Setting
Address
Bits
Bit Name
Description
0x0501
7
Enable 3.3 V CMOS driver
0 (default) = disables 3.3 V CMOS driver; the OUT5 1.8 V logic is controlled by Register 0x0501[6:4].
1 = enables 3.3 V CMOS driver as operating mode of OUT0.
This bit should be enabled only if Bits[6:4] are in CMOS mode.
[6:4]
OUT0 format
This control is valid when Register 0x0501[7] = 0.
When Register 0x0501[7] = 1, OUT5 is in 3.3 V CMOS mode and these bits are ignored.
Select the operating mode of OUT0.
000 = PD, tristate.
001 (default) = HSTL.
010 = LVDS.
011 = reserved.
100 = CMOS, both outputs active.
101 = CMOS, P output active, N output power-down.
110 = CMOS, N output active, P output power-down.
111 = reserved.
[3:2]
OUT0 polarity
Control the OUT0 polarity.
00 (default) = positive, negative.
01 = positive, positive.
10 = negative, positive.
11 = negative, nevative.
1
OUT0 drive strength
Controls the output drive capability of OUT0.
0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.
1 = CMOS: normal drive strength; LVDS: 4.5 mA nominal (LVDS boost mode).
Note that this is only in 3.3 V CMOS mode for CMOS strength.
1.8 V CMOS has only the low drive strength.
0
Enable OUT0
Enables/disables (1b/0b) OUT0 1.8 V driver (default is disabled).
This bit does not enable/disable OUT0 if Bit 7 of this register is set.
Table 69. Distribution Channel 0 Divider Setting
Address
Bits
Bit Name
Description
0x0502
[7:0]
Channel 0 (M0)
division ratio
10-bit channel divider bits[7:0] (LSB).
Division equals channel divider, Bits[9:0] + 1.
(Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2…Bits[9:0] = 1023 is divide-by-1024)
0x0503
[7:4]
Reserved
Reserved.
3
Channel 0 PD
0 (default) = normal operation.
1 = powers down Channel 0.
2
Select RF Divider 2
1 = selects RF Divider 2 as prescaler for Channel 0 divider.
0 (default) = selects RF Divider 1 as prescaler for Channel 0 divider.
[1:0]
Channel 0 (M0)
division ratio
10-bit channel divider, Bits[9:8] (MSB)
0x0504
[7:6]
Reserved
Reserved. Default: 00b
[5:0]
Channel 0 divider phase
Divider initial phase after sync relative to the divider input clock (from the RF divider
output). LSB is of a period of the divider input clock. Default: 00000b.
Phase = 0 is no phase offset.
Phase = 1 is a period offset.
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