- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1987 > AD9551BCPZ (Analog Devices Inc)IC CLOCK GEN MULTISERV 40-LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9551BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN MULTISERV 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
AD9551
Rev. B | Page 22 of 40
The value of K depends on the device configuration, as shown
in Table 16.
Table 16. Configuring the Value of K
Mode
fCRYSTAL
K
Description
19.44 MHz
52 MHz
1300/243
Using 2× multiplier
325/243
Using 2× divider
50 MHz
1250/243
Using 2× multiplier
625/486
Using 2× divider
49.86 MHz
277/54
Using 2× multiplier
277/216
Using 2× divider
49.152 MHz
2048/405
Using 2× multiplier
512/405
Using 2× divider
Normal
1
Crystal independent
The user must carefully consider the operating frequency of the
externally connected crystal resonator (assuming that the input
PLL is not bypassed). Because the DCXO is capable of pulling
the crystal over a 50 ppm range only, the output frequency of
the DCXO is essentially identical to the crystal frequency.
The denominator of Equation 1 is the input division factor, which
has an integer part (Nx) due to an integer divider, as well as an
optional fractional part that is associated with the input SDM.
1/2 + FRACx/(2 × MODx)
Note that when bypassing the SDM, the device forces the frac-
tional part to 0 (equivalent to FRACx = MODx).
The numerator of Equation 2 contains the feedback division
factor, which has an integer part (N) due to an integer divider,
as well as an optional fractional part (FRAC/MOD) that is
associated with the feedback SDM.
Equation 1 and Equation 2, along with the constraints placed on
their variables, imply a rational relationship between fREF and fOUT1.
That is, the ratio fOUT1/fREF must be expressible as a ratio of two
integers. For example, it is not possible to configure the device
to satisfy a frequency ratio having a value of 2 because it is
irrational (that is, not expressible as a ratio of two integers).
CALCULATING DIVIDER VALUES
This section provides a 5-step procedure for calculating the divider
values when given a specific fOUT1/fREF ratio. The methodology is
described in general terms, but a specific example is provided
for clarity. The example assumes the use of the frequency control
pins with A[3:0] = 0010 and Y[3:0] = 0100 (see Table 13 and
Table 14). The example parameters are as follows:
MHz
239
08
.
622
237
=
f
REF
MHz
64
625
=
OUT1
f
MHz
26
=
IF
f
66
Calculation Steps
1.
Ensure that fOUT1 and fREF are rationally related.
As shown in the following equation, fOUT1/fREF is expressible
as a ratio of two integers, so fOUT1 and fREF are rationally related.
568
553
,
951
,
977
)
64
)(
239
(
62208
)
100
)(
237
)(
66
(
625
237
239
08
.
622
64
66
625
=
=
REF
OUT1
f
,
000
,
625
2.
Determine the output divide factor (ODF).
Note that the VCO frequency (fVCO) spans 3350 MHz to
4050 MHz. The ratio, fVCO/fOUT1, indicates the required ODF.
Given the specified value of fOUT1 (~644.53 MHz) and the
range of fVCO, the ODF spans a range of 5.2 to 6.3. The ODF
must be an integer, which means that ODF = 6 (because 6
is the only integer between 5.2 and 6.3).
3.
Determine suitable values for P0 and P1.
The ODF is the product of the two output dividers; that is,
ODF = P0 × P1. It has already been determined that ODF = 6
for the given example. Therefore, we have P0 × P1 = 6, with the
constraints that P0 and P1 are both integers and that 4 ≤ P0 ≤ 11
(see the Output/Input Frequency Relationship section).
These constraints lead to the singular solution of P0 = 6, and P1
= 1.
Although this particular example yields a singular solution
for the output divider values with fOUT1 ≈ 644.53 MHz, some
fOUT1 frequencies result in multiple ODFs rather than just
one. For example, if fOUT1 = 100 MHz, the ODF ranges from
34 to 40. This leads to an assortment of possible values for
valid. However, note that they yield only three valid ODF
values (35, 36, and 40) from the original range of 34 to 40.
Table 17. Combinations of P0 and P1
P0
P1
ODF
4
9
36
4
10
40
5
7
35
5
8
40
6
36
7
5
35
8
5
40
9
4
36
10
4
40
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9552BCPZ-REEL7 | IC PLL CLOCK GEN LP 32LFCSP |
| AD9553BCPZ-REEL7 | IC INTEGER-N CLCK GEN 32LFCSP |
| AD9557BCPZ-REEL7 | IC CLK XLATR PLL 1250MHZ 40LFCSP |
| AD9558BCPZ-REEL7 | IC CLK XLATR PLL 1250MHZ 64LFCSP |
| AD9571ACPZPEC-R7 | IC PLL CLOCK GEN 25MHZ 40LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9551BCPZ-REEL7 | 功能描述:IC CLOCK GEN TRANSLATOR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9552 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Oscillator Frequency Upconverter |
| AD9552/PCBZ | 功能描述:BOARD EVALUATION FOR AD9552 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9552BCPZ | 功能描述:IC PLL CLOCK GEN LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9552BCPZ | 制造商:Analog Devices 功能描述:IC PLL CLOCK GENERATOR 112.5MHZ LFCSP-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。