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AD9550
Rev. 0 | Page 14 of 20
Y5 to Y0
f
VCO (MHz)
f
OUT1 (MHz)
f
OUT2 (MHz)
P
0
P
1
P
2
011101
3732.48
155.52
77.76
6
4
8
011110
3732.48
155.52
19.44
6
4
32
011111
3732.48
77.76
6
8
100000
3732.48
77.76
19.44
6
8
32
100001
3732.48
19.44
6
32
100010
3686.4
153.6
6
4
100011
3686.4
153.6
122.88
6
4
5
100100
3686.4
153.6
61.44
6
4
10
100101
3686.4
153.6
2.048
6
4
300
100110
3686.4
153.6
1.536
6
4
400
100111
3600
100
6
101000
3600
100
50
6
12
101001
3600
100
25
6
24
101010
3600
50
6
12
101011
3600
50
25
6
12
24
101100
3705.6
1.544
6
400
101101
~3985.53
f
f
6
1
101110
~3985.53
f
f
6
1
2
101111
~3985.53
f
f
6
1
4
110000
~3985.53
f
f
6
2
110001
~3985.53
f
f
6
2
4
110010
~3985.53
f
f
6
4
110011
3732.48
622.08
6
1
110100 to 111110
Undefined
111111
3750
125
25
5
6
30
1
fO = 39,191.04/59 MHz.
Table 8. Pin Configuration vs. PLL Feedback Divider Value and Charge Pump Value
A3 to A0
Y5 to Y0
0001 to 1100
000001 to 010101
230,400
121
010110 to 011011
234,375
121
011100 to 100001
233,280
121
100010 to 100110
230,400
121
100111 to 101011
225,000
121
101100
231,600
121
101101 to 111111
Undefined
1101
000001 to 101100
Undefined
101101 to 110010
1512
255
110010 to 111111
Undefined
1110
000001 to 110010
Undefined
110011
768
121
110100 to 111110
Undefined
111111
2400
121
1111
000001 to 010101
276,480
145
010110 to 011011
281,250
145
011100 to 100001
279,936
145
100010 to 100110
276,480
145
100111 to 101011
270,000
145
101100
277,920
145
101101 to 111111
Undefined
1 PLL feedback divider value (decimal).
2 Charge pump value (decimal). Multiply by 3.5 A to yield I
CP.