參數(shù)資料
型號(hào)： AD9523BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/60頁(yè)
文件大小： 0K
描述： IC INTEGER-N CLCK GEN 72LFCSP
標(biāo)準(zhǔn)包裝： 400
類型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配）
PLL： 是
主要目的： 以太網(wǎng)，光纖通道，SONET/SDH
輸入： CMOS
輸出： HSTL，LVCMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP-VQ（10x10）
包裝： 帶卷 (TR)
配用： AD9523/PCBZ-ND - BOARD EVAL FOR AD9523
Data Sheet
AD9523
Rev. C | Page 13 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LDO_PLL1
VDD3_PLL1
REFA
REFB
LF1_EXT_CAP
OSC_CTRL
OSC_IN
LF2_EXT_CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
PD
REF_SEL
17
SYNC
18
VDD3_REF
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
R
ESET
CS
SC
L
K
/SC
L
S
D
IO/S
D
A
SD
O
R
E
F_
TE
S
T
OU
T
1
3
OU
T
1
3
V
DD3_
O
UT
[1
2:
1
3
]
OU
T
1
2
OU
T
1
2
V
D
D1.
8
_
O
UT
[1
2
:13
]
OU
T
1
OU
T
1
V
DD3_
O
UT
[1
0:
1
]
OU
T
1
0
35
OU
T
1
0
36
V
D
D1.
8
_
O
UT
[1
0
:1
1
]
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VDD1.8_OUT[4:5]
OUT4
VDD3_OUT[4:5]
OUT5
VDD1.8_OUT[6:7]
OUT6
VDD3_OUT[6:7]
OUT7
VDD1.8_OUT[8:9]
OUT8
VDD3_OUT[8:9]
OUT9
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
PL
L
1
_
O
U
T
ZD
_
IN
ZD
_
IN
NC
OU
T
0
OU
T
0
V
DD3_
O
UT
[0
:1
]
OU
T
1
OU
T
1
V
DD1.
8_O
UT
[0
:3
]
OU
T
2
OU
T
2
V
DD3_
O
UT
[2
:3
]
OU
T
3
OU
T
3
EEPR
O
M
_
SE
L
ST
A
T
U
S
0
/SP0
ST
A
T
U
S
1
/SP1
08
439
-00
2
PIN 1
INDICATOR
AD9523
(TOP VIEW)
NOTES
1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.
AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT.
ON EXISTING PCB DESIGNS, IT ISACCEPTABLE TO LEAVE PIN 69 CONNECTED TO 1.8V SUPPLY.
2. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE
SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY
AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 2. Pin Configuration
Table 19. Pin Function Descriptions
Pin
No.
Mnemonic
Type1
Description
1
LDO_PLL1
P/O
1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 μF decoupling capacitor from
this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in
close proximity to the device.
2
VDD3_PLL1
P
3.3 V Supply PLL1. Use the same supply as VCXO.
3
REFA
I
Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
4
REFA
I
Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the
PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.
5
REFB
I
Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
6
REFB
I
Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
7
LF1_EXT_CAP
O
PLL1 External Loop Filter Capacitor. Connect a loop filter capacitor to this pin and to ground.
8
OSC_CTRL
O
Oscillator Control Voltage. Connect this pin to the voltage control pin of the external oscillator.
9
OSC_IN
I
PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
10
OSC_IN
I
Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
11
LF2_EXT_CAP
O
PLL2 External Loop Filter Capacitor Connection. Connect a capacitor to this pin and LDO_VCO.
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