- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1987 > AD9522-5BCPZ (Analog Devices Inc)IC CLOCK GEN 2.4GHZ 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9522-5BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 68/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.4GHZ 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當(dāng)前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
AD9522-5
Rev. 0 | Page 70 of 76
Reg.
Addr
(Hex) Bit(s) Name
Description
194
[4]
Divider 1 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
194
[3:0]
Divider 1 phase offset
Phase offset (default: 0x0).
195
[2]
Channel 1 power-down
Channel 1 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into the high
impedance power-down mode by setting this bit.)
195
[0]
Disable Divider 1 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
196
[7:4]
Divider 2 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1).
196
[3:0]
Divider 2 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1).
197
[7]
Divider 2 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
197
[6]
Divider 2 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
197
[5]
Divider 2 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
197
[4]
Divider 2 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
197
[3:0]
Divider 2 phase offset
Phase offset (default: 0x0).
198
[2]
Channel 2 power-down
Channel 2 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into the high
impedance power-down mode by setting this bit.)
198
[0]
Disable Divider 2 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
199
[7:4]
Divider 3 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x0 means the divider is low for one input clock cycle (default: 0x0).
199
[3:0]
Divider 3 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x0 means the divider is high for one input clock cycle (default: 0x0).
19A
[7]
Divider 3 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
19A
[6]
Divider 3 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
19A
[5]
Divider 3 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
19A
[4]
Divider 3 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
19A
[3:0]
Divider 3 phase offset
Phase offset (default: 0x0).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9523-1BCPZ-REEL7 | IC INTEGER-N CLCK GEN 72LFCSP |
| AD9523BCPZ | IC INTEGER-N CLCK GEN 72LFCSP |
| AD9524BCPZ | IC INTEGER-N CLCK GEN 48LFCSP |
| AD9540BCPZ-REEL7 | IC CLOCK GEN/SYNTHESIZER 48LFCSP |
| AD9547BCPZ-REEL7 | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9522-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.4GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9523 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs |
| AD9523/PCBZ | 功能描述:BOARD EVAL FOR AD9523 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9523-1/PCBZ | 功能描述:BOARD EVAL FOR AD9523-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9523-1BCPZ | 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。