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參數(shù)資料
| 型號： | AD9522-1BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9522-1
Rev. 0 | Page 67 of 84
Table 52. PLL
Reg.
Addr
(Hex) Bit(s) Name
Description
010
[7]
PFD polarity
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only.
The on-chip VCO requires positive polarity, [7] = 0.
[7] = 0; positive (higher control voltage produces higher frequency) (default).
[7] = 1; negative (higher control voltage produces lower frequency).
010
[6:4]
CP current
Charge pump current (with CPRSET = 5.1 kΩ).
[6]
[5]
[4]
ICP (mA)
0
0.6
0
1
1.2
0
1
0
1.8
0
1
2.4
1
0
3.0
1
0
1
3.6
1
0
4.2
1
4.8 (default)
010
[3:2]
CP mode
Charge pump operating mode.
[3]
[2]
Charge Pump Mode
0
High impedance state.
0
1
Force source current (pump up).
1
0
Force sink current (pump down).
1
Normal operation (default).
010
[1:0]
PLL power-
down
PLL operating mode.
[1]
[0]
Mode
0
Normal operation; this mode must be selected to use the PLL.
0
1
Asynchronous power-down (default).
1
0
Unused.
1
Synchronous power-down.
011
[7:0]
14-bit R counter,
Bits[7:0] (LSB)
Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is
14 bits long. The lower eight bits are in this register (default: 0x01).
012
[5:0]
14-bit R counter,
Bits[13:8] (MSB)
Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is
14 bits long. The upper six bits are in this register (default: 0x00).
013
[5:0]
6-bit A counter
A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00).
014
[7:0]
13-bit B counter,
Bits[7:0] (LSB)
B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03).
015
[4:0]
13-bit B counter,
Bits[12:8] (MSB)
B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00).
016
[7]
Set CP pin
to VCP/2
Sets the CP pin to one-half of the VCP supply voltage.
[7] = 0; CP normal operation (default).
[7] = 1; CP pin set to VCP/2.
016
[6]
Reset R counter
Reset R counter (R divider).
[6] = 0; normal (default).
[6] = 1; hold R counter in reset.
016
[5]
Reset A and B
counters
Reset A and B counters (part of N divider).
[5] = 0; normal (default).
[5] = 1; hold A and B counters in reset.
016
[4]
Reset all
counters
Reset R, A, and B counters.
[4] = 0; normal (default).
[4] = 1; hold R, A, and B counters in reset.
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