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| 型號： | AD9522-1/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 63/84頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9522-1 CLK GEN |
| 設計資源： | AD9522 Eval Board Schematic AD9522 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9522-1 |
| 主要屬性： | 12 LVDS/24 CMOS 輸出，2.4 GHz VCO |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板 |
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AD9522-1
Rev. 0 | Page 66 of 84
REGISTER MAP DESCRIPTIONS
Table 49 through Table 59 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and
[5:2] refers to the range of bits from Bit 5 through Bit 2.
Table 49. SPI Mode Serial Port Configuration
Reg Addr (Hex)
Bit(s)
Name
Description
000
[7]
SDO active
Selects unidirectional or bidirectional data transfer mode.
[7] = 0; SDIO pin used for write and read; SDO is high impedance (default).
[7] = 1; SDO used for read; SDIO used for write; unidirectional mode.
000
[6]
LSB first/addr incr
SPI MSB or LSB data orientation. (This register is ignored in I2C mode.)
[6] = 0; data-oriented MSB first; addressing decrements (default).
[6] = 1; data-oriented LSB first; addressing increments.
000
[5]
Soft reset
Soft reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit
self-clears on the next SCLK cycle after the completion of writing to this register.
000
[4]
Unused
000
[3:0]
Mirror[7:4]
Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part
is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
004
[0]
Readback active registers
Select register bank used for a readback.
[0] = 0; read back buffer registers (default).
[0] = 1; read back active registers.
Table 50. I2C Mode Serial Port Configuration
Reg Addr (Hex)
Bit(s)
Name
Description
000
[7:6]
Unused
000
[5]
Soft reset
Soft reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit
self-clears on the next SCL cycle after the completion of writing to this register.
000
[4]
Unused
000
[3:0]
Mirror[7:4]
Bits[3:0] should always mirror Bits[7:4]. Set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
004
[0]
Readback active registers
Select register bank used for a readback.
[0] = 0; read back buffer registers (default).
[0] = 1; read back active registers.
Table 51. EEPROM ID
Reg Addr (Hex)
Bit(s)
Name
Description
005
[7:0]
EEPROM customer
version ID (LSB)
16-bit EEPROM ID[7:0]. This register, along with 0x006, allows the user to store a
unique ID to identify which version of the AD9522 register settings is stored in the
EEPROM. It does not affect AD9522 operation in any way (default: 0x00).
006
[7:0]
EEPROM customer
version ID (MSB)
16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a
unique ID to identify which version of the AD9522 register settings is stored in the
EEPROM. It does not affect AD9522 operation in any way (default: 0x00).
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