
AD9516-3
Data Sheet
Rev. C | Page 18 of 80
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
15, 18, 19, 20
N/A
NC
No Connect. Do not connect to this pin.
16
I
3.3 V CMOS
SCLK
Serial Control Port Data Clock Signal.
17
I
3.3 V CMOS
CS
Serial Control Port Chip Select, Active Low. This pin has an internal 30 k pull-up
resistor.
21
O
3.3 V CMOS
SDO
Serial Control Port Unidirectional Serial Data Out.
22
I/O
3.3 V CMOS
SDIO
Serial Control Port Bidirectional Serial Data In/Out.
23
I
3.3 V CMOS
RESET
Chip Reset, Active Low. This pin has an internal 30 k pull-up resistor.
24
I
3.3 V CMOS
PD
Chip Power-Down, Active Low. This pin has an internal 30 k pull-up resistor.
27, 41, 54
I
Power
VS_LVPECL
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
37, 44, 59,
EPAD
N/A
GND
Ground Pins, Including External Paddle (EPAD). The external paddle on the bottom of
the package must be connected to ground for proper operation.
56
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
55
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
53
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
52
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
43
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
42
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
40
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
39
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
25
O
LVPECL
OUT4
LVPECL Output; One Side of a Differential LVPECL Output.
26
O
LVPECL
OUT4
LVPECL Output; One Side of a Differential LVPECL Output.
28
O
LVPECL
OUT5
LVPECL Output; One Side of a Differential LVPECL Output.
29
O
LVPECL
OUT5
LVPECL Output; One Side of a Differential LVPECL Output.
48
O
LVDS or
CMOS
OUT6
(OUT6A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
47
O
LVDS or
CMOS
OUT6
(OUT6B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
46
O
LVDS or
CMOS
OUT7
(OUT7A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
45
O
LVDS or
CMOS
OUT7
(OUT7B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
33
O
LVDS or
CMOS
OUT8
(OUT8A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
34
O
LVDS or
CMOS
OUT8
(OUT8B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
35
O
LVDS or
CMOS
OUT9
(OUT9A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
36
O
LVDS or
CMOS
OUT9
(OUT9B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
58
O
Current set
resistor
RSET
A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 k.
62
O
Current set
resistor
CPRSET
A resistor connected to this pin sets the CP current range. Nominal value = 5.1 k.
63
I
Reference
input
REFIN
(REF2)
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
64
I
Reference
input
REFIN
(REF1)
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.